ATMEGA3250-16AUR Atmel, ATMEGA3250-16AUR Datasheet - Page 202

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ATMEGA3250-16AUR

Manufacturer Part Number
ATMEGA3250-16AUR
Description
MCU AVR 32K FLASH 16MHZ 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA3250-16AUR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA3250-16AUR
Manufacturer:
Atmel
Quantity:
10 000
22.2
2570M–AVR–04/11
Operation
Figure 22-1. Analog to Digital Converter Block Schematic
The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-
mation. The minimum value represents GND and the maximum value represents the voltage on
the AREF pin minus 1 LSB. Optionally, AVCC or an internal 1.1V reference voltage may be con-
nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal
voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve
noise immunity.
The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input
pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended
inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Volt-
age reference and input channel selections will not go into effect until ADEN is set. The ADC
does not consume power when ADEN is cleared, so it is recommended to switch off the ADC
before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
AREF
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
AVCC
GND
REFERENCE
REFERENCE
INTERNAL
8-BIT DATA BUS
BANDGAP
INPUT
INPUT
POS.
NEG.
MUX
MUX
ADC MULTIPLEXER
SELECT (ADMUX)
MUX DECODER
+
-
SINGLE ENDED / DIFFERENTIAL SELECTION
DIFFERENTIAL
AMPLIFIER
ATmega325/3250/645/6450
10-BIT DAC
ADC CTRL. & STATUS
REGISTER (ADCSRA)
ADC CONVERSION
COMPLETE IRQ
PRESCALER
CONVERSION LOGIC
ADTS[2:0]
INTERRUPT
TRIGGER
SELECT
FLAGS
SAMPLE & HOLD
COMPARATOR
15
+
-
ADC DATA REGISTER
(ADCH/ADCL)
ADC MULTIPLEXER
OUTPUT
0
202

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