ATMEGA3250-16AUR Atmel, ATMEGA3250-16AUR Datasheet - Page 280

• Manufacturer Part Number: ATMEGA3250-16AUR
• Description: MCU AVR 32K FLASH 16MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3250-16AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.7
26.7.1
2570M–AVR–04/11
Serial Downloading
Serial Programming Pin Mapping
Table 26-12. Parallel Programming Characteristics, V
Notes:
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
Table 26-13. Pin Mapping Serial Programming
Figure 26-10. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Symbol
t
t
t
BVDV
OLDV
OHDZ
Symbol
1. t
2. t
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
MOSI
MISO
SCK
commands.
XTAL1 pin.
WLRH
WLRH_CE
CC
Parameter
BS1 Valid to DATA valid
OE Low to DATA Valid
OE High to DATA Tri-stated
- 0.3V < AVCC < V
is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
is valid for the Chip Erase command.
Pins
PB2
PB3
PB1
CC
MOSI
MISO
SCK
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
RESET
XTAL1
GND
I/O
O
ATmega325/3250/645/6450
I
I
(1)
AVCC
VCC
CC
+1.8 - 5.5V
+1.8 - 5.5V
= 5V ± 10% (Continued)
Min
0
(2)
Table 26-13 on page
Serial Data out
Serial Data in
Description
Serial Clock
Typ
Max
250
250
250
Units
ns
ns
ns
280, the pin
280