PIC18F26J50-I/SP Microchip Technology, PIC18F26J50-I/SP Datasheet - Page 161

• Manufacturer Part Number: PIC18F26J50-I/SP
• Description: IC PIC MCU FLASH 64K 2V 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26J50-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART/I2C/SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.2
The TMR1CS bit of the T1CON register is used to
select the clock source. When TMR1CS = 0, the clock
source is F
is supplied externally.
13.2.1
When the internal clock source is selected, the
TMR1H:TMR1L register pair will increment on multiples
of T
13.2.2
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
When counting, Timer1 is incremented on the rising
edge of the external clock input T1CKI. In addition, the
Counter mode clock can be synchronized to the
microcontroller system clock or run asynchronously.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC without CLKOUT),
Timer1 can use the LP oscillator as a clock source.
FIGURE 13-3:
© 2008 Microchip Technology Inc.
Note:
CY
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
as determined by the Timer1 prescaler.
Note 1: Arrows indicate counter increments.
Clock Source Selection
OSC
• Timer1 is enabled after POR or BOR
• A write to TMR1H or TMR1L
• Timer1 is disabled (TMR1ON = 0)
INTERNAL CLOCK SOURCE
EXTERNAL CLOCK SOURCE
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after one or more
of the following conditions (see Figure 13-3):
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of
Reset
when T1CKI is high then Timer1 is
enabled (TMR1ON = 1) when T1CKI
is low.
/4. When TMR1CS = 1, the clock source
the clock.
TIMER1 INCREMENTING EDGE
Preliminary
13.2.3
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TTMR1L register
pair.
13.3
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
13.4
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
continues to increment asynchronous to the internal
phase clocks. The timer will continue to run during
Sleep and can generate an interrupt on overflow,
which will wake-up the processor. However, special
precautions in software are needed to read/write the
timer (see Section 13.2.3 “Reading and Writing
Timer1 in Asynchronous Counter Mode”).
PIC18F2XK20/4XK20
Note 1: When switching from synchronous to
Timer1 Prescaler
Timer1 Operation in
Asynchronous Counter Mode
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
DS41303D-page 159