PIC18F26J50-I/SP Microchip Technology, PIC18F26J50-I/SP Datasheet - Page 81

• Manufacturer Part Number: PIC18F26J50-I/SP
• Description: IC PIC MCU FLASH 64K 2V 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26J50-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART/I2C/SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 5-2:
© 2008 Microchip Technology Inc.
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEADRH
EEDATA
EECON2
EECON1
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE
TRISD
TRISC
TRISB
TRISA
LATE
LATD
LATC
LATB
LATA
PORTE
PORTD
PORTC
PORTB
PORTA
ANSELH
ANSEL
IOCB
WPUB
CM1CON0
CM2CON0
CM2CON1
SLRCON
SSPMSK
Legend:
Note
File Name
(2)
(2)
(2)
(2)
(2)
1:
2:
3:
4:
5:
6:
7:
(6)
(7)
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.2 “PLL in
HFINTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices.
EUSART Transmit Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
EUSART Receive Register
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
PORTD Data Direction Control Register
PORTC Data Direction Control Register
PORTB Data Direction Control Register
PORTD Data Latch Register (Read and Write to Data Latch)
PORTC Data Latch Register (Read and Write to Data Latch)
PORTB Data Latch Register (Read and Write to Data Latch)
TRISA7
MC1OUT
EEADR7
PSPIP
PSPIE
PSPIF
LATA7
OSCFIP
OSCFIF
OSCFIE
INTSRC
ANS7
EEPGD
WPUB7
RA7
IOCB7
CSRC
SPEN
C1ON
C2ON
MSK7
Bit 7
RD7
RC7
RB7
IBF
—
—
—
—
—
(5)
REGISTER FILE SUMMARY (PIC18F2XK20/4XK20) (CONTINUED)
(2)
(2)
(2)
(2)
(5)
(5)
TRISA6
MC2OUT
PLLEN
EEADR6
LATA6
ANS6
WPUB6
C1OUT
C2OUT
IOCB6
RA6
CFGS
MSK6
ADIP
ADIF
ADIE
Bit 6
C1IP
C1IF
C1IE
RX9
OBF
RD6
RC6
RB6
TX9
—
—
—
—
—
(5)
(2)
(5)
(3)
(5)
Data Direction Control Register for PORTA
PORTA Data Latch Register (Read and Write to Data Latch)
EEADR5
C1RSEL
ANS5
WPUB5
IOCB5
SREN
C1OE
C2OE
MSK5
TXEN
TUN5
RCIP
RCIE
IBOV
C2IP
C2IE
RCIF
Bit 5
C2IF
RD5
RC5
RB5
RA5
—
—
—
—
—
—
(2)
PSPMODE
EEADR4
C2RSEL
WPUB4
SLRE
C1POL
C2POL
ANS12
IOCB4
SYNC
CREN
FREE
MSK4
TUN4
ANS4
Bit 4
EEIP
EEIF
EEIE
TXIP
TXIF
TXIE
RD4
RC4
RB4
RA4
—
—
—
Preliminary
(2)
EEADR3
WRERR
SLRD
ADDEN
WPUB3
SENDB
ANS11
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
RE3
TUN3
ANS3
C1SP
C2SP
MSK3
Bit 3
RD3
RC3
RB3
RA3
—
—
—
—
—
(4)
(2)
PIC18F2XK20/4XK20
PORTE Data Latch Register
(Read and Write to Data Latch)
EEADR2
CCP1IP
CCP1IF
CCP1IE
WPUB2
HLVDIP
HLVDIF
HLVDIE
TRISE2
WREN
ANS10
BRGH
RE2
FERR
MSK2
TUN2
ANS2
SLRC
Bit 2
RD2
RC2
C1R
C2R
RB2
RA2
—
—
—
(2)
EEADR1
EEADR9
TMR3IP
TMR3IE
TMR2IP
TMR2IE
TMR3IF
TMR2IF
TRISE1
WPUB1
C1CH1
C2CH1
OERR
RE1
TRMT
MSK1
TUN1
ANS9
ANS1
SLRB
Bit 1
RD1
RC1
RB1
RA1
WR
—
—
(2)
EEADR0
EEADR8
CCP2IP
CCP2IE
TMR1IP
TMR1IF
TMR1IE
CCP2IF
TRISE0
WPUB0
C1CH0
C2CH0
RE0
RX9D
TUN0
ANS8
ANS0
SLRA
MSK0
TX9D
Bit 0
RD0
RC0
RB0
RA0
RD
—
—
(2)
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000 59, 88, 97
---- --00 59, 88, 97
0000 0000 59, 88, 97
0000 0000 59, 88, 97
xx-0 x000 59, 89, 97
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
0q00 0000
0000 -111
1111 1111
1111 1111
1111 1111
1111 1111
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- x000
xxxx xxxx
xxxx xxxx
xxx0 0000
xx0x 0000
---1 1111
1111 1111
0000 ----
1111 1111
0000 0000
0000 0000
0000 ----
---1 1111
1111 1111
POR, BOR
DS41303D-page 79
Value on
on page:
Details
59, 237
59, 237
59, 234
59, 233
59, 242
59, 243
60, 115
60, 113
60, 114
60, 110
60, 112
60, 132
60, 128
60, 125
60, 122
60, 119
60, 131
60, 128
60, 125
60, 122
60, 119
60, 131
60, 128
60, 125
60, 122
60, 119
60, 135
60, 134
60, 122
60, 122
60, 280
60, 281
61, 283
61, 136
61, 211
60, 111
31, 60