PIC18F26J50-I/SP Microchip Technology, PIC18F26J50-I/SP Datasheet - Page 399

• Manufacturer Part Number: PIC18F26J50-I/SP
• Description: IC PIC MCU FLASH 64K 2V 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26J50-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART/I2C/SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 26-22:
TABLE 26-25: A/D CONVERSION REQUIREMENTS
© 2008 Microchip Technology Inc.
130
131
132
135
136
Legend: TBD = To Be Determined
Note 1:
Param
No.
2:
3:
4:
A/D DATA
Note 1:
SAMPLE
A/D CLK
T
T
T
T
T
ADRES
Symbol
BSF ADCON0, GO
AD
CNV
ACQ
SWC
DIS
ADIF
The time of the A/D clock period is dependent on the device frequency and the T
ADRES register may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
Ω.
On the following cycle of the device clock.
GO
2:
Q4
If the A/D clock source is selected as RC, a time of T
This allows the SLEEP instruction to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
A/D Clock Period
Conversion Time
(not including acquisition time) (Note 2)
Acquisition Time (Note 3)
Switching Time from Convert → Sample
Discharge Time
132
A/D CONVERSION TIMING
(Note 2)
Characteristic
DD
9
to V
SS
8
or V
OLD_DATA
SS
7
Preliminary
to V
.. .
SAMPLING STOPPED
DD
CY
). The source impedance (R
CY
is added before the A/D clock starts.
cycle.
. . .
131
130
PIC18F2XK20/4XK20
TBD
TBD
Min
0.7
0.7
1.4
0.2
11
—
2
(Note 4)
25.0
4.0
TBD
Max
12
—
—
—
(1)
(1)
1
Units
T
μs
μs
μs
μs
μs
μs
AD
S
) on the input channels is 50
0
T
-40°C to +85°C
T
+125°C
A/D RC mode
-40°C to +85°C
0°C ≤ to ≤ +85°C
OSC
OSC
AD
based, V
based, V
clock divider.
NEW_DATA
DONE
Conditions
DS41303D-page 397
T
CY
REF
REF
≥ 3.0V,
≥ 3.0V,