PIC18F26J50-I/SP Microchip Technology, PIC18F26J50-I/SP Datasheet - Page 341

• Manufacturer Part Number: PIC18F26J50-I/SP
• Description: IC PIC MCU FLASH 64K 2V 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26J50-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART/I2C/SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NEGF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2008 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
=
=
register ‘f’
Negate f
NEGF
0 ≤ f ≤ 255
a ∈ [0,1]
( f ) + 1 → f
N, OV, C, DC, Z
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
NEGF
Read
0110
Q2
0011 1010 [3Ah]
1100 0110 [C6h]
f {,a}
REG, 1
110a
Process
Data
Q3
ffff
register ‘f’
Write
Q4
ffff
Preliminary
NOP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
None.
PIC18F2XK20/4XK20
Q Cycle Activity:
Decode
Q1
operation
No Operation
NOP
None
No operation
None
No operation.
1
1
0000
1111
Q2
No
0000
xxxx
operation
Q3
No
DS41303D-page 339
0000
xxxx
operation
Q4
No
0000
xxxx