PIC18F26J50-I/SP Microchip Technology, PIC18F26J50-I/SP Datasheet - Page 92

• Manufacturer Part Number: PIC18F26J50-I/SP
• Description: IC PIC MCU FLASH 64K 2V 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26J50-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART/I2C/SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2XK20/4XK20
6.2.2
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
6.2.3
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 6-2. These operations on the TBLPTR affect only
the low-order 21 bits.
6.2.4
TBLPTR is used in reads, writes and erases of the
Flash program memory.
TABLE 6-2:
FIGURE 6-3:
DS41303D-page 90
TBLRD*
TBLWT*
TBLRD*+
TBLWT*+
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
Example
Note 1: n = 3, 4, 5, or 6 for block sizes of 8, 16, 32 or 64 bytes, respectively.
21
TABLAT – TABLE LATCH REGISTER
TBLPTR – TABLE POINTER
REGISTER
TABLE POINTER BOUNDARIES
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
TBLPTRU
TABLE POINTER BOUNDARIES BASED ON OPERATION
16
15
TABLE ERASE/WRITE
TBLPTR<21:n+1>
TBLPTR is incremented before the read/write
TBLPTR is decremented after the read/write
TABLE READ – TBLPTR<21:0>
TBLPTR is incremented after the read/write
TBLPTRH
Preliminary
Operation on Table Pointer
(1)
TBLPTR is not modified
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
directly into the TABLAT register.
When a TBLWT is executed the byte in the TABLAT reg-
ister is written, not to Flash memory but, to a holding
register in preparation for a program memory write. The
holding registers constitute a write block which varies
depending on the device (See Table 6-1).The 3, 4, or 5
LSbs of the TBLPTRL register determine which specific
address within the holding register block is written to.
The MSBs of the Table Pointer have no effect during
TBLWT operations.
When a program memory write is executed the entire
holding register block is written to the Flash memory at
the address determined by the MSbs of the TBLPTR.
The 3, 4, or 5 LSBs are ignored during Flash memory
writes. For more detail, see Section 6.5 “Writing to
Flash Program Memory”.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
8
7
TBLPTRL
© 2008 Microchip Technology Inc.
TBLPTR<n:0>
TABLE WRITE
(1)
0