PIC18F26J50-I/SP Microchip Technology, PIC18F26J50-I/SP Datasheet - Page 420

• Manufacturer Part Number: PIC18F26J50-I/SP
• Description: IC PIC MCU FLASH 64K 2V 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26J50-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART/I2C/SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2XK20/4XK20
Extended Instruction Set
F
Fail-Safe Clock Monitor .............................................. 38, 295
Fast Register Stack ............................................................ 66
Firmware Instructions ....................................................... 311
Flash Program Memory ...................................................... 87
G
General Call Address Support ......................................... 216
GOTO ............................................................................... 332
H
Hardware Multiplier .......................................................... 103
High/Low-Voltage Detect ................................................. 289
DS41303D-page 418
Interrupts
Synchronous Master Mode .............................. 253, 258
Synchronous Slave Mode
ADDFSR .................................................................. 354
ADDULNK ................................................................ 354
and Using MPLAB Tools .......................................... 360
CALLW ..................................................................... 355
Considerations for Use ............................................ 358
MOVSF .................................................................... 355
MOVSS .................................................................... 356
PUSHL ..................................................................... 356
SUBFSR .................................................................. 357
SUBULNK ................................................................ 357
Syntax ...................................................................... 353
Fail-Safe Condition Clearing ...................................... 38
Fail-Safe Detection .................................................... 38
Fail-Safe Operation .................................................... 38
Reset or Wake-up from Sleep .................................... 38
Associated Registers ................................................. 95
Control Registers ....................................................... 88
Erase Sequence ........................................................ 92
Erasing ....................................................................... 92
Operation During Code-Protect ................................. 95
Reading ...................................................................... 91
Table Pointer
Table Pointer Boundaries .......................................... 90
Table Reads and Table Writes .................................. 87
Write Sequence ......................................................... 93
Writing To ................................................................... 93
Introduction .............................................................. 103
Operation ................................................................. 103
Performance Comparison ........................................ 103
Applications .............................................................. 293
Associated Registers ............................................... 293
Characteristics ......................................................... 377
Asychronous Receive ...................................... 239
Asychronous Transmit ..................................... 235
Associated Registers, Receive ........................ 257
Associated Registers, Transmit ............... 255, 258
Reception ......................................................... 256
Transmission .................................................... 253
Associated Registers, Receive ........................ 259
Reception ......................................................... 259
Transmission .................................................... 258
EECON1 and EECON2 ..................................... 88
TABLAT (Table Latch) Register ......................... 90
TBLPTR (Table Pointer) Register ...................... 90
Boundaries Based on Operation ........................ 90
Protection Against Spurious Writes ................... 95
Unexpected Termination .................................... 95
Write Verify ........................................................ 95
Preliminary
HLVD. See High/Low-Voltage Detect. ............................. 289
HLVDCON Register ......................................................... 289
I
I/O Ports ........................................................................... 119
I
I
ID Locations ............................................................. 295, 309
INCF ................................................................................ 332
INCFSZ ............................................................................ 333
In-Circuit Debugger .......................................................... 309
In-Circuit Serial Programming (ICSP) ...................... 295, 309
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 358
Indirect Addressing ............................................................ 82
INFSNZ ............................................................................ 333
Initialization Conditions for all Registers ...................... 57–60
Instruction Cycle ................................................................ 67
Instruction Flow/Pipelining ................................................. 67
Instruction Set .................................................................. 311
2
2
C
C Mode (MSSP)
Current Consumption ............................................... 291
Effects of a Reset .................................................... 293
Operation ................................................................. 290
Setup ....................................................................... 291
Start-up Time ........................................................... 291
Typical Application ................................................... 293
Associated Registers ............................................... 232
Acknowledge Sequence Timing .............................. 226
Baud Rate Generator .............................................. 219
Bus Collision
Clock Arbitration ...................................................... 220
Clock Stretching ....................................................... 212
Clock Synchronization and the CKP bit (SEN = 1) .. 213
Effects of a Reset .................................................... 227
General Call Address Support ................................. 216
I
Master Mode ............................................................ 217
Multi-Master Communication, Bus Collision and
Multi-Master Mode ................................................... 227
Operation ................................................................. 205
Read/Write Bit Information (R/W Bit) ............... 205, 206
Registers ................................................................. 200
Serial Clock (RC3/SCK/SCL) ................................... 206
Slave Mode .............................................................. 205
Sleep Operation ....................................................... 227
Stop Condition Timing ............................................. 226
and Standard PIC18 Instructions ............................. 358
Clocking Scheme ....................................................... 67
ADDLW .................................................................... 317
ADDWF .................................................................... 317
2
C Clock Rate w/BRG ............................................. 219
During Sleep .................................................... 293
During a Repeated Start Condition .................. 230
During a Stop Condition .................................. 231
10-Bit Slave Receive Mode (SEN = 1) ............ 212
10-Bit Slave Transmit Mode ............................ 212
7-Bit Slave Receive Mode (SEN = 1) .............. 212
7-Bit Slave Transmit Mode .............................. 212
Operation ......................................................... 218
Reception ........................................................ 223
Repeated Start Condition Timing .................... 222
Start Condition Timing ..................................... 221
Transmission ................................................... 223
Arbitration ........................................................ 227
Addressing ....................................................... 205
Reception ........................................................ 206
Transmission ................................................... 206
© 2008 Microchip Technology Inc.