AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 239

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.13 Slave Mode
19.13.1
19.13.2
Figure 19-23. Slave Mode Typical Application Block Diagram
19.13.3
19.13.4
19.13.4.1
32059J–12/2010
Definition
Application Block Diagram
Programming Slave Mode
Receiving Data
Read Sequence
Host with
Interface
Master
TWI
The Slave Mode is defined as a mode where the device receives the clock and the address from
another device called the master.
In this mode, the device never initiates and never completes the transmission (START,
REPEATED_START and STOP conditions are always provided by the master).
The following fields must be programmed before entering Slave mode:
1. SADR (SMR): The slave device address is used in order to be accessed by master
2. MSDIS (CR): Disable the master mode.
3. SVEN (CR): Enable the slave mode.
As the device receives the clock, values written in CWGR are not taken into account.
After a Start or Repeated Start condition is detected and if the address sent by the Master
matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave
ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer.
SVACC remains high until a STOP condition or a repeated START is detected. When such a
condition is detected, EOSACC (End Of Slave ACCess) flag is set.
In the case of a Read sequence (SVREAD is high), TWI transfers data written in the THR (TWI
Transmit Holding Register) until a STOP condition or a REPEATED_START + an address differ-
ent from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission
Complete) flag is set and SVACC reset.
TWD
TWCK
devices in read or write mode.
Host with TWI
Interface
Slave 1
Host with TWI
Interface
Slave 2
LCD Controller
Slave 3
R
R
AT32UC3B
VDD
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