AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 428

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.8.2.2
Register Name:
Access Type:
Offset:
Reset Value:
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32059J–12/2010
DMAnINT: DMA Channel n Interrupt
EPnINT: Endpoint n Interrupt
UPRSM: Upstream Resume Interrupt
EORSM: End of Resume Interrupt
WAKEUP: Wake-Up Interrupt
EORST: End of Reset Interrupt
SOF: Start of Frame Interrupt
EP3INT
31
23
15
7
-
-
-
This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if DMAnINTE is one.
This bit is cleared when the UDDMAnSTATUS interrupt source is cleared.
This bit is set when an interrupt is triggered by the endpoint n (UESTAn, UECONn). This triggers a USB interrupt if EPnINTE is
This bit is cleared when the interrupt source is serviced.
This bit is set when the USBB sends a resume signal called “Upstream Resume”. This triggers a USB interrupt if UPRSME is
This bit is cleared when the UDINTCLR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be
This bit is set when the USBB detects a valid “End of Resume” signal initiated by the host. This triggers a USB interrupt if
This bit is cleared when the UDINTCLR.EORSMC bit is written to one to acknowledge the interrupt.
This bit is set when the USBB is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This
This bit is cleared when the UDINTCLR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock inputs must be
This bit is cleared when the Suspend (SUSP) interrupt bit is set.
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
This bit is set when a USB “End of Reset” has been detected. This triggers a USB interrupt if EORSTE is one.
This bit is cleared when the UDINTCLR.EORSTC bit is written to one to acknowledge the interrupt.
This bit is set when a USB “Start of Frame” PID (SOF) has been detected (every 1 ms). This triggers a USB interrupt if SOFE is
This bit is cleared when the UDINTCLR.SOFC bit is written to one to acknowledge the interrupt.
one.
one.
enabled before).
EORSME is one.
triggers an interrupt if WAKEUPE is one.
enabled before).
one. The FNUM field is updated.
Device Global Interrupt Register
DMA6INT
UPRSM
EP2INT
30
22
14
6
-
UDINT
Read-Only
0x0004
0x00000000
DMA5INT
EORSM
EP1INT
29
21
13
5
-
DMA4INT
WAKEUP
EP0INT
28
20
12
4
-
DMA3INT
EORST
27
19
11
3
-
-
DMA2INT
EP6INT
SOF
26
18
10
2
-
DMA1INT
EP5INT
25
17
9
1
-
-
AT32UC3B
EP4INT
SUSP
24
16
8
0
-
-
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