AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 248

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.14.1
Name:
Access:
Offset:
Reset Value: 0x00000000
•
•
•
•
•
•
•
32059J–12/2010
SWRST: Software Reset
SVDIS: TWI Slave Mode Disabled
SVEN: TWI Slave Mode Enabled
MSDIS: TWI Master Mode Disabled
MSEN: TWI Master Mode Enabled
STOP: Send a STOP Condition
START: Send a START Condition
SWRST
31
23
15
–
–
–
7
0 = No effect.
1 = Equivalent to a system reset.
0 = No effect.
1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation.
0 = No effect.
1 = If SVDIS = 0, the slave mode is enabled.
Switching from Master to Slave mode is only permitted when TXCOMP = 1.
0 = No effect.
1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are
0 = No effect.
1 = If MSDIS = 0, the master mode is enabled.
Switching from Slave to Master mode is only permitted when TXCOMP = 1.
0 = No effect.
1 = STOP Condition is sent just after completing the current byte transmission in master read mode.
0 = No effect.
- In single data byte master read, the START and STOP must both be set.
- In multiple data bytes master read, the STOP must be set after the last data received but one.
- In master read mode, if a NACK bit is received, the STOP is automatically performed.
- In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent.
In write operation, the character being transferred must be completely received before disabling.
transmitted in case of write operation. In read operation, the character being transferred must be completely received before
disabling.
Control Register
CR
Write-only
0x00
30
22
14
–
–
–
6
–
SVDIS
29
21
13
–
–
–
5
SVEN
28
20
12
–
–
–
4
MSDIS
27
19
11
–
–
–
3
MSEN
26
18
10
–
–
–
2
STOP
25
17
–
–
9
–
1
AT32UC3B
START
24
16
–
–
8
–
0
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