AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 442

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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32059J–12/2010
RXSTPI: Received SETUP Interrupt
RXOUTI: Received OUT Data Interrupt
TXINI: Transmitted IN Data Interrupt
This bit is set, for control endpoints, to signal that the current bank contains a new valid SETUP packet. This triggers an EPnINT
Shall be cleared by writing a one to the RXSTPIC bit. This will acknowledge the interrupt and free the bank.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means UNDERFI for isochronous IN/OUT endpoints.
This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers an
Shall be cleared for control end points, by writing a one to the RXOUTIC bit. This will acknowledge the interrupt and free the
This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as FIFOCON when the current bank is full.
Shall be cleared for isochronous, bulk and, interrupt OUT endpoints, by writing a one to the RXOUTIC bit. This will acknowledge
The user then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT endpoint is composed of multiple
RXOUTI shall always be cleared before clearing FIFOCON.
This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.
This bit is set for control endpoints, when the current bank is ready to accept a new IN packet. This triggers an EPnINT interrupt
This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt and send the packet.
This bit is set for isochronous, bulk and interrupt IN endpoints, at the same time as FIFOCON when the current bank is free.
This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt, what has no effect on the endpoint
The user then writes into the FIFO and clears the FIFOCON bit to allow the USBB to send the data. If the IN endpoint is
TXINI shall always be cleared before clearing FIFOCON.
This bit is inactive (cleared) for isochronous, bulk and interrupt OUT endpoints.
interrupt if RXSTPE is one.
EPnINT interrupt if RXOUTE is one.
bank.
This triggers an EPnINT interrupt if RXOUTE is one.
the interrupt, what has no effect on the endpoint FIFO.
banks, this also switches to the next bank. The RXOUTI and FIFOCON bits are set/cleared in accordance with the status of
the next bank.
if TXINE is one.
This triggers an EPnINT interrupt if TXINE is one.
FIFO.
composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are set/cleared in accordance
with the status of the next bank.
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