AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 254

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.14.6
Name:
Access:
Offset:
Reset Value: 0x0000F009
•
•
•
•
•
•
•
•
32059J–12/2010
TXBUFE: TX Buffer Empty
RXBUFF: RX Buffer Full
ENDTX: End of TX buffer
ENDRX: End of RX buffer
EOSACC: End Of Slave Access (clear on read)
SCLWS: Clock Wait State (automatically set / reset)
ARBLST: Arbitration Lost (clear on read)
NACK: Not Acknowledged (clear on read)
TXBUFE
31
23
15
–
–
7
–
This bit is only used in Master mode.
0 = TCR or TNCR have a value other than 0.
1 = Both TCR and TNCR have a value of 0.
This bit is only used in Master mode.
0 = RCR or RNCR have a value other than 0.
1 = Both RCR and RNCR have a value of 0.
This bit is only used in Master mode.
0 = The Transmit Counter Register has not reached 0 since the last write in TCR or TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in TCR or TNCR.
This bit is only used in Master mode.
0 = The Receive Counter Register has not reached 0 since the last write in RCR or RNCR.
1 = The Receive Counter Register has reached 0 since the last write in RCR or RNCR.
This bit is only used in Slave mode.
0 = A slave access is being performing.
1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset.
EOSACC behavior can be seen in
This bit is only used in Slave mode.
0 = The clock is not stretched.
1 = The clock is stretched. THR / RHR buffer is not filled / emptied before the emission / reception of a new character.
SCLWS behavior can be seen in
This bit is only used in Master mode.
0 = Arbitration won.
1 = Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.
Status Register
SR
Read-only
0x20
RXBUFF
OVRE
30
22
14
–
–
6
ENDTX
GACC
29
21
13
–
–
5
Figure 19-27 on page 243
Figure 19-29 on page 245
ENDRX
SVACC
28
20
12
–
–
4
and
and
EOSACC
SVREAD
Figure 19-28 on page
Figure 19-30 on page 245
27
19
11
–
–
3
SCLWS
TXRDY
26
18
10
–
–
2
244.
ARBLST
RXRDY
25
17
–
–
9
1
AT32UC3B
TXCOMP
NACK
24
16
–
–
8
0
254