AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 455

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.8.3.2
Register Name:
Access Type:
Offset:
Reset Value:
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32059J–12/2010
DMAnINT: DMA Channel n Interrupt
PnINT: Pipe n Interrupt
HWUPI: Host Wake-Up Interrupt
HSOFI: Host Start of Frame Interrupt
RXRSMI: Upstream Resume Received Interrupt
RSMEDI: Downstream Resume Sent Interrupt
RSTI: USB Reset Sent Interrupt
DDISCI: Device Disconnection Interrupt
31
23
15
7
-
-
-
-
This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if the corresponding
This bit is cleared when the UHDMAnSTATUS interrupt source is cleared.
This bit is set when an interrupt is triggered by the endpoint n (UPSTAn). This triggers a USB interrupt if the corresponding pipe
This bit is cleared when the interrupt source is served.
This bit is set when the host controller is in the suspend mode (SOFE is zero) and an upstream resume from the peripheral is
This bit is set when the host controller is in the suspend mode (SOFE is zero) and a peripheral disconnection is detected.
This bit is set when the host controller is in the Idle state (USBSTA.VBUSRQ is zero, no VBus is generated).
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
This bit is set when a SOF is issued by the Host controller. This triggers a USB interrupt when HSOFE is one. When using the
This bit is cleared when the HSOFIC bit is written to one.
This bit is set when an Upstream Resume has been received from the Device.
This bit is cleared when the RXRSMIC is written to one.
This bit set when a Downstream Resume has been sent to the Device.
This bit is cleared when the RSMEDIC bit is written to one.
This bit is set when a USB Reset has been sent to the device.
This bit is cleared when the RSTIC bit is written to one.
This bit is set when the device has been removed from the USB bus.
This bit is cleared when the DDISCIC bit is written to one.
DMAnINTE is one (UHINTE register).
interrupt enable bit is one (UHINTE register).
detected.
host controller in low speed mode, this bit is also set when a keep-alive is sent.
Host Global Interrupt Register
DMA6INT
HWUPI
P6INT
30
22
14
6
-
UHINT
Read-Only
0x0404
0x00000000
DMA5INT
HSOFI
P5INT
29
21
13
5
-
DMA4INT
RXRSMI
P4INT
28
20
12
4
-
DMA3INT
RSMEDI
P3INT
27
19
11
3
-
DMA2INT
P2INT
RSTI
26
18
10
2
-
DMA1INT
DDISCI
P1INT
25
17
9
1
-
AT32UC3B
DCONNI
P0INT
24
16
8
0
-
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