AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 554

IC MCU AVR32 512K FLASH 64QFN

AT32UC3B0512-Z2UR

Manufacturer Part Number
AT32UC3B0512-Z2UR
Description
IC MCU AVR32 512K FLASH 64QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3B0512-Z2UR

Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
96K x 8
Program Memory Size
512KB (512K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B0512-Z2UR
Manufacturer:
ATMEL
Quantity:
2 010
25.6.4
Figure 25-2. EOCn and DRDY Flag Behavior
32059J–12/2010
CHn(CHSR)
DRDY(SR)
EOCn(SR)
Conversion Results
With START=1
Write CR
(CDRn). The two highest bits of the DATA field in the corresponding CDRn register will be read
as zero. The two highest bits of the Last Data Converted field in the Last Converted Data Regis-
ter (LCDR.LDATA) will be read as zero too.
Moreover, when a Peripheral DMA channel is connected to the ADC, a 10-bit resolution sets the
transfer request size to 16-bit. Writing a one to the LOWRES bit automatically switches to 8-bit
data transfers. In this case, the destination buffers are optimized.
When a conversion is completed, the resulting 10-bit digital value is stored in the CDR register of
the current channel and in the LCDR register. Channels are enabled by writing a one to the
Channel n Enable bit (CHn) in the CHER register.
The corresponding channel End of Conversion bit in the Status Register (SR.EOCn) and the
Data Ready bit in the SR register (SR.DRDY) are set. In the case of a connected Peripheral
DMA channel, DRDY rising triggers a data transfer request. In any case, either EOC or DRDY
can trigger an interrupt.
Reading one of the CDRn registers clears the corresponding EOC bit. Reading LCDR clears the
DRDY bit and the EOC bit corresponding to the last converted channel.
Conversion Time
Read CDRn
With START=1
Write CR
Conversion Time
AT32UC3B
Read LCDR
554

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