AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 445

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.8.2.14
Register Name:
Access Type:
Offset:
Reset Value:
•
•
•
•
32059J–12/2010
STALLRQ: STALL Request
RSTDT: Reset Data Toggle
EPDISHDMA: Endpoint Interrupts Disable HDMA Request Enable
FIFOCON: FIFO Control
PACKETE
SHORT
31
23
15
7
-
-
-
This bit is set when the STALLRQS bit is written to one. This will request to send a STALL handshake to the host.
This bit is cleared when a new SETUP packet is received or when the STALLRQC bit is written to zero.
This bit is set when the RSTDTS bit is written to one. This will clear the data toggle sequence, i.e., set to Data0 the data toggle
This bit is cleared instantaneously.
The user does not have to wait for this bit to be cleared.
This bit is set when the EPDISHDMAS is written to one. This will pause the on-going DMA channel n transfer on any Endpoint n
The user then has to acknowledge or to disable the interrupt source (e.g. RXOUTI) or to clear the EPDISHDMA bit (by writing a
In ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is
If the interrupt is not associated to a new system-bank packet (NAKINI, NAKOUTI, etc.), then the request cancellation may
This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to complete a
For control endpoints:
The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints. When read,
For IN endpoints:
This bit is set when the current bank is free, at the same time as TXINI.
This bit is cleared (by writing a one to the FIFOCONC bit) to send the FIFO data and to switch to the next bank.
For OUT endpoints:
This bit is set when the current bank is full, at the same time as RXOUTI.
sequence of the next sent (IN endpoints) or received (OUT endpoints) packet.
interrupt (EPnINT), whatever the state of the Endpoint n Interrupt Enable bit (EPnINTE).
one to the EPDISHDMAC bit) in order to complete the DMA transfer.
running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet DMA
transfer will not start (not requested).
occur at any time and may immediately pause the current DMA transfer.
DMA transfer by software after reception of a short packet, etc.
their value is always 0.
Endpoint n Control Register
STALLEDE/
CRCERRE
FIFOCON
30
22
14
6
-
-
UECONn, n in [0..6]
Read-Only
0x01C0 + (n * 0x04)
0x00000000
OVERFE
KILLBK
29
21
13
5
-
-
NBUSYBKE
NAKINE
28
20
12
4
-
-
NAKOUTE
STALLRQ
27
19
11
3
-
-
UNDERFE
RXSTPE/
RSTDT
26
18
10
2
-
-
RXOUTE
25
17
9
1
-
-
-
AT32UC3B
EPDISHDMA
TXINE
24
16
8
0
-
-
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