AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 446

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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32059J–12/2010
KILLBK: Kill IN Bank
NBUSYBKE: Number of Busy Banks Interrupt Enable
SHORTPACKETE: Short Packet Interrupt Enable
STALLEDE: STALLed Interrupt Enable
CRCERRE: CRC Error Interrupt Enable
OVERFE: Overflow Interrupt Enable
NAKINE: NAKed IN Interrupt Enable
NAKOUTE: NAKed OUT Interrupt Enable
RXSTPE: Received SETUP Interrupt Enable
UNDERFE: Underflow Interrupt Enable
RXOUTE: Received OUT Data Interrupt Enable
TXINE: Transmitted IN Data Interrupt Enable
This bit is cleared (by writing a one to the FIFOCONC bit) to free the current bank and to switch to the next bank.
This bit is set when the KILLBKS bit is written to one. This will kill the last written bank.
This bit is cleared by hardware after the completion of the “kill packet procedure”.
The user shall wait for this bit to be cleared before trying to process another IN packet.
Caution: The bank is cleared when the “kill packet” procedure is completed by the USBB core :
If the bank is really killed, the NBUSYBK field is decremented.
If the bank is not “killed” but sent (IN transfer), the NBUSYBK field is decremented and the TXINI flag is set. This specific case
Note : If two banks are ready to be sent, the above specific case can not occur, because the first bank is sent (IN transfer) while
This bit is set when the NBUSYBKES bit is written to one. This will enable the Number of Busy Banks interrupt (NBUSYBK).
This bit is cleared when the NBUSYBKEC bit is written to zero. This will disable the Number of Busy Banks interrupt
This bit is set when the SHORTPACKETES bit is written to one. This will enable the Short Packet interrupt (SHORTPACKET).
This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Short Packet interrupt
This bit is set when the STALLEDES bit is written to one. This will enable the STALLed interrupt (STALLEDI).
This bit is cleared when the STALLEDEC bit is written to one. This will disable the STALLed interrupt (STALLEDI).
This bit is set when the CRCERRES bit is written to one. This will enable the CRC Error interrupt (CRCERRI).
This bit is cleared when the CRCERREC bit is written to one. This will disable the CRC Error interrupt (CRCERRI).
This bit is set when the OVERFES bit is written to one. This will enable the Overflow interrupt (OVERFI).
This bit is cleared when the OVERFEC bit is written to one. This will disable the Overflow interrupt (OVERFI).
This bit is set when the NAKINES bit is written to one. This will enable the NAKed IN interrupt (NAKINI).
This bit is cleared when the NAKINEC bit is written to one. This will disable the NAKed IN interrupt (NAKINI).
This bit is set when the NAKOUTES bit is written to one. This will enable the NAKed OUT interrupt (NAKOUTI).
This bit is cleared when the NAKOUTEC bit is written to one. This will disable the NAKed OUT interrupt (NAKOUTI).
This bit is set when the RXSTPES bit is written to one. This will enable the Received SETUP interrupt (RXSTPI).
This bit is cleared when the RXSTPEC bit is written to one. This will disable the Received SETUP interrupt (RXSTPI).
This bit is set when the UNDERFES bit is written to one. This will enable the Underflow interrupt (UNDERFI).
This bit is cleared when the UNDERFEC bit is written to one. This will disable the Underflow interrupt (UNDERFI).
This bit is set when the RXOUTES bit is written to one. This will enable the Received OUT Data interrupt (RXOUT).
This bit is cleared when the RXOUTEC bit is written to one. This will disable the Received OUT Data interrupt (RXOUT).
This bit is set when the TXINES bit is written to one. This will enable the Transmitted IN Data interrupt (TXINI).
This bit is cleared when the TXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXINI).
can occur if at the same time an IN token is coming and the user wants to kill this bank.
the last bank is killed.
(NBUSYBK).
(SHORTPACKET).
AT32UC3B
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