ST7FLITEU09M3 STMicroelectronics, ST7FLITEU09M3 Datasheet - Page 118

• Manufacturer Part Number: ST7FLITEU09M3
• Description: IC MCU 8BIT 2K FLASH 8SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU09M3

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Electrical characteristics
13.10
Table 69.
1. Unless otherwise specified, typical data are based on T
2. The maximum ADC clock frequency allowed within V
118/139
Symbol
C
t
R
f
V
t
STAB
ADC
ADC
guidelines and are not tested.
ADC
AIN
AIN
ADC clock frequency
Conversion voltage range
External input resistor
Internal sample and hold
capacitor
Stabilization time after ADC
enable
Conversion time (sample+hold)
- Sample capacitor loading time
- Hold conversion time
Figure 67. RESET pin protection when LVD is disabled
1. Please refer to
2. The reset network protects the device against parasitic resets.
10-bit ADC characteristics
Subject to general operating condition for V
ADC characteristics
The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin
can go below the V
taken into account internally.
Because the reset circuit is designed to allow the internal Reset to be output in the RESET pin, the user
must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for
I
INJ(RESET)
Required
EXTERNAL
CIRCUIT
RESET
USER
Parameter
in
Table 46 on page
Section 12.2.1 on page 92
(2)
IL
0.01 F
max. level specified in
V
V
2.7 V V
f
2.4 V V
f
f
f
96.
ADC
ADC
CPU
ADC
DD
DD
DD
= 5 V, f
= 3.3 V, f
= 2 MHz
= 1 MHz
= 8 MHz,
= 4 MHz
A
= 2.4 V to 2.7 V operating range is 1 MHz.
=25 °C and V
DD
DD
Conditions
for more details on illegal opcode reset conditions.
V
Section 13.9.1 on page
ADC
DD
5.5 V,
2.7 V,
ADC
R
= 4 MHz
ON
DD
= 4 MHz
Filter
, f
DD
OSC
-V
GENERATOR
SS
, and T
PULSE
= 5 V. They are given only as design
116. Otherwise the reset will not be
Min
V
A
SS
unless otherwise specified.
ST7LITEU05 ST7LITEU09
Typ
0
3.5
10
3
4
(4)
(1)
WATCHDOG
ILLEGAL OPCODE
10k
20k
INTERNAL
RESET
8k
7k
Max
V
4
DD
(3)
(3)
(3)
(3)
ST72XXX
1/f
MHz
Unit
1)
pF
V
ADC
s