ST7FLITEU09M3 STMicroelectronics, ST7FLITEU09M3 Datasheet - Page 24

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ST7FLITEU09M3

Manufacturer Part Number
ST7FLITEU09M3
Description
IC MCU 8BIT 2K FLASH 8SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FLITEU09M3

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
ST7FLITEUx
Core
ST7
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
ICC
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
5
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
 Details

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Data EEPROM
5.3.2
Note:
24/139
On this device, data EEPROM can also be used to execute machine code. Take care not to
write to the data EEPROM while executing from it. This would result in an unexpected code
being executed.
Write operation (E2LAT=1)
To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains
cleared). When a write access to the EEPROM area occurs, the value is latched inside the
32 data latches according to its address.
When PGM bit is set by the software, all the previous bytes written in the data latches (up to
32) are programmed in the EEPROM cells. The effective high address (row) is determined
by the last EEPROM write sequence. To avoid wrong programming, the user must take care
that all the bytes written between two programming sequences have the same high address:
only the five Least Significant Bits of the address can change.
At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.
Care should be taken during the programming cycle. Writing to the same memory location
will over-program the memory (logical AND between the two write access data result)
because the data latches are only cleared at the end of the programming cycle and by the
falling edge of the E2LAT bit. It is not possible to read the latched data.
This note is ilustrated by the
Figure 8.
Data EEPROM programming flowchart
IN EEPROM AREA
READ MODE
READ BYTES
E2PGM=0
CLEARED BY HARDWARE
E2LAT=0
Figure
10.
(with the same 11 MSB of the address)
START PROGRAMMING CYCLE
E2PGM=1 (set by software)
WRITE UP TO 32 BYTES
0
IN EEPROM AREA
WRITE MODE
E2PGM=0
E2LAT=1
E2LAT=1
E2LAT
1
ST7LITEU05 ST7LITEU09

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