ST7FLITEU09M3 STMicroelectronics, ST7FLITEU09M3 Datasheet - Page 84

• Manufacturer Part Number: ST7FLITEU09M3
• Description: IC MCU 8BIT 2K FLASH 8SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU09M3

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Details

On-chip peripherals
11.3.4
Note:
11.3.5
11.3.6
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Low power modes
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Table 33.
Interrupts
None.
Register description
ADC Control/status register (ADCCSR)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of conversion
Bit 6 = SPEED ADC clock selection
Bit 5 = ADON A/D converter on
Bits 4:3 = Reserved. Must be kept cleared.
Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They select the analog input to convert.
EOC
This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH
register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
This bit is set and cleared by software. It is used together with the SLOW bit to
configure the ADC clock speed. Refer to the table in the SLOW bit description.
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
7
Mode
Wait
Halt
Effect of low power modes
SPEED
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Converter requires a stabilization time
t
performed.
STAB
(see Electrical Characteristics) before accurate conversions can be
ADON
Read/Write (Except bit 7 read only)
0
Description
0
CH2
ST7LITEU05 ST7LITEU09
CH1
CH0
0