ST7FLITEU09M3 STMicroelectronics, ST7FLITEU09M3 Datasheet - Page 48

• Manufacturer Part Number: ST7FLITEU09M3
• Description: IC MCU 8BIT 2K FLASH 8SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU09M3

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Interrupts
Note:
8.4.3
Table 12.
48/139
Wait
Halt
Mode
Monitoring the V
The AVD threshold is selected by the AVD[1:0] bits in the AVDTHCR register.
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the
V
In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing
software to shut down safely before the LVD resets the microcontroller. See
The interrupt on the rising edge is used to inform the application that the V
is over
Make sure the right combination of LVD and AVD thresholds is used as LVD and AVD levels
are not correlated. Refer to
more details.
Figure 21. Using the AVD to monitor V
Low power modes
Description of low power modes
Interrupts
The AVD interrupt event generates an interrupt if the corresponding enable control bit
(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
AVDF bit
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
IT+(AVD)
LVD RESET
V
V
V
V
IT+(AVD)
IT+(LVD)
IT-(LVD)
IT-(AVD)
No effect on SI. AVD interrupts cause the device to exit from Wait mode.
The SICSR register is frozen.
The AVD remains active but the AVD interrupt cannot be used to exit from Halt mode.
or V
V
DD
IT-(AVD)
0
DD
threshold (AVDF bit is set).
main supply.
1
Section 13.3.2 on page 98
INTERRUPT Cleared by
V
Early warning interrupt
(Power has dropped, MCU not
not yet in reset)
hyst
reset
RESET
DD
Description
and
1
Section 13.3.3 on page 98
INTERRUPT Cleared by
ST7LITEU05 ST7LITEU09
hardware
0
DD
Figure
warning state
21.
for