ST7FLITE49K2T6TR STMicroelectronics, ST7FLITE49K2T6TR Datasheet - Page 51

• Manufacturer Part Number: ST7FLITE49K2T6TR
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE49K2
7.5.3
System integrity (SI) control/status register (SICSR)
Reset value: 011x 0x00 (xxh)
Bit 7 = Reserved, must be kept cleared
Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits
Bit 4 = WDGRF Watchdog Reset flag
This bit indicates that the last reset was generated by the watchdog peripheral. It is set by
hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to
ensure a stable cleared state of the WDGRF flag when CPU starts). The WDGRF and the
LVDRF flags areis used to select the reset source (see
page
Table 10.
Bit 3 = Reserved, must be kept cleared
Bit 2 = LVDRF LVD reset flag
Bit 1 = AVDF Voltage detector flag
0
7
These bits, as well as CR[9:2] bits in the RCCR register must be written immediately
after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. Refer
to
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled
by option byte, the LVDRF bit value is undefined.
The LVDRF flag is not cleared when another RESET type occurs (external or
watchdog), the LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can
not.
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt
request is generated when the AVDF bit is set. Refer to
additional details.
0: V
1: V
51).
Section 7.1.1: Internal RC oscillator on page
DD
DD
CR1
over AVD threshold
under AVD threshold
Reset source selection
External RESET pin
CR0
RESET source
Watchdog
LVD
WDGRF
Read/write
0
Supply, reset and clock management
38.
Table 10: Reset source selection on
LVDRF
Figure 19
LVDRF
0
0
1
and to
AVDF
Section
WDGRF
0
1
X
AVDIE
0
51/245
for