W78E516DPG Nuvoton Technology Corporation of America, W78E516DPG Datasheet - Page 29

• Manufacturer Part Number: W78E516DPG
• Description: IC MCU 8-BIT 64K FLASH 44-PLCC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E516DPG

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

External Interrupt Control
Mnemonic: XICON
Port 4 control A
Mnemonic: P4CONA
1
0
Bit:
BIT
7
6
5
4
3
2
1
0
Bit:
BIT
7,6
FBOOTSL
FPROGEN
NAME
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
NAME
P41FUN1
P41FUN0
7
PX3
7
P41FUN1
6
6
EX3
P41FUN0
FUNCTION
External interrupt 3 priority high if set
External interrupt 3 enable if set
If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is
detected/serviced
External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared
by software
External interrupt 2 priority high if set
External interrupt 2 enable if set
If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is
detected/serviced
External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared
by software
FUNCTION
00: Mode 0. P4.1 is a general purpose I/O port which is the same as Port1.
01: Mode 1. P4.1is a Read Strobe signal for chip select purpose. The address
range depends on the SFR P41AH, P41AL, P41CMP1 and P41CMP0.
10: Mode 2. P4.1 is a Write Strobe signal for chip select purpose. The address
Preliminary W78E516D/ W78E058D Data Sheet
5
IE3
5
P41CMP1
1: Enable. The microcontroller switches to the programming flash
mode after entering the idle mode and waken up from interrupt.
The microcontroller will execute the loader program while in on-
chip programming mode.
0: Disable. The on-chip flash memory is read-only. In-system
0: Disable the on-chip AUX-RAM
The Loader Program Location Select.
0: The Loader Program locates at the 64K/32K Byte flash memory
bank.
1: The Loader Program locates at the 4KB flash memory bank.
Flash EPROM Programming Enable
programmability is disabled.
4
IT3
4
P41CMP0
- 29 -
3
PX2
3
P40FUN1
Publication Release Date: July 30, 2008
2
EX2
2
P40FUN0
1
IE2
1
P40CMP1
Address: C0h
Address: C2h
Revision A01
0
IT2
0
P40CMP0