W78E516DPG Nuvoton Technology Corporation of America, W78E516DPG Datasheet - Page 47

• Manufacturer Part Number: W78E516DPG
• Description: IC MCU 8-BIT 64K FLASH 44-PLCC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E516DPG

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

13 RESET CONDITIONS
The user has several hardware related options for placing the W78E516D/W78E058D into reset
condition. In general, most register bits go to their reset value irrespective of the reset condition, but
there are a few flags whose state depends on the source of reset. The user can use these flags to
determine the cause of reset using software.
13.1 Sources of reset
The device continuously samples the RST pin at state S5P2 of every machine cycle. Therefore the
RST pin must be held for at least 2 machine cycles to ensure detection of a valid RST low. The reset
circuitry then synchronously applies the internal reset signal. Thus the reset is a synchronous
operation and requires the clock to be running to cause an external reset.
Once the device is in reset condition, it will remain so as long as RST is 0. Even after RST is
deactivated, the device will continue to be in reset state for up to two machine cycles, and then begin
program execution from 0000h. There is no flag associated with the external reset condition. However
since the other two reset sources have flags, the external reset can be considered as the default reset
if those two flags are cleared.
The software must clear the POR flag after reading it. Otherwise it will not be possible to correctly
determine future reset sources. If the power fails, i.e. falls below Vrst, then the device will once again
go into reset state. When the power returns to the proper operating levels, the device will again
perform a power on reset delay and set the POR flag.
The W78E516D/W78E058D offers a software reset to switch back to the AP Flash EPROM. Setting
CHPCON bits 0, 1 and 7 to logic-1 creates a software reset to reset the CPU.
Most of the SFRs and registers on the device will go to the same condition in the reset state. The
Program Counter is forced to 0000h and is held there as long as the reset condition is applied.
However, the reset state does not affect the on-chip RAM. The data in the RAM will be preserved
during the reset. However, the stack pointer is reset to 07h, and therefore the stack contents will be
lost. The RAM contents will be lost if the VDD falls below approximately 2V, as this is the minimum
voltage level required for the RAM to operate normally. Therefore after a first time power on reset the
RAM contents will be indeterminate. During a power fail condition, if the power falls below 2V, the
RAM contents are lost.
After a reset most SFRs are cleared. Interrupts and Timers are disabled. The Watchdog timer is
disabled if the reset source was a POR. The port SFRs have FFh written into them which puts the port
pins in a high state.
13.1.1 External Reset
13.1.2 Software Reset
13.1.3 RESET STATE
Preliminary W78E516D/ W78E058D Data Sheet
- 47 -
Publication Release Date: July 30, 2008
Revision A01