W78E516DPG Nuvoton Technology Corporation of America, W78E516DPG Datasheet - Page 50

• Manufacturer Part Number: W78E516DPG
• Description: IC MCU 8-BIT 64K FLASH 44-PLCC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E516DPG

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

determines which request is serviced. This is called the arbitration ranking. Note that the arbitration
ranking is only used to resolve simultaneous requests of the same priority level.
Table below summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits,
arbitration ranking, and external interrupt may wake up the CPU from Power Down mode.
13.4 Interrupt Response Time
The response time for each interrupt source depends on several factors, such as the nature of the
interrupt and the instruction underway. In the case of external interrupts INT0 and INT1 , they are
sampled at S5P2 of every machine cycle and then their corresponding interrupt flags IEx will be set or
reset. The Timer 0 and 1 overflow flags are set at C3 of the machine cycle in which overflow has
occurred. These flag values are polled only in the next machine cycle. If a request is active and all
three conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes
four machine cycles to be completed. Thus there is a minimum time of five machine cycles between
the interrupt flag being set and the interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
service routine currently being executed. If the polling cycle is not the last machine cycle of the
instruction being executed, then an additional delay is introduced. The maximum response time (if no
other interrupt is in service) occurs if the device is performing a write to IE, IP and then executes a
MUL or DIV instruction. From the time an interrupt source is activated, the longest reaction time is 12
machine cycles. This includes 1 machine cycle to detect the interrupt, 2 machine cycles to complete
the IE, IP access, 5 machine cycles to complete the MUL or DIV instruction and 4 machine cycles to
complete the hardware LCALL to the interrupt vector location.
Source
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port
Timer 2
Overflow/Match
External Interrupt 2
External Interrupt 3
Flag
IE0
TF0
IE1
TF1
RI + TI
TF2
XICON
XICON
Preliminary W78E516D/W78E058D Data Sheet
Table 13- 2 Summary of interrupt sources
Vector
address
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
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Enable bit
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ES (IE.4)
ET2 (IE.5)
EX2
(XICON.2)
EX3
(XICON.6)
Flag
cleared by
Hardware,
software
Hardware,
software
Hardware,
software
Hardware,
software
Software
Software
Hardware,
software
Hardware,
software
Arbitration
ranking
1(highest)
2
3
4
5
6
7
8(lowest)
Yes
Yes
Power-
down
wakeup
No
Yes
No
No
No
Yes