W78E516DPG Nuvoton Technology Corporation of America, W78E516DPG Datasheet - Page 51

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W78E516DPG

Manufacturer Part Number
W78E516DPG
Description
IC MCU 8-BIT 64K FLASH 44-PLCC
Manufacturer
Nuvoton Technology Corporation of America
Series
W78r
Datasheet

Specifications of W78E516DPG

Core Processor
8052
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

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Preliminary W78E516D/ W78E058D Data Sheet
Thus in a single-interrupt system the interrupt response time will always be more than 5 machine
cycles and not more than 12 machine cycles. The maximum latency of 12 machine cycle is 48 clock
cycles. Note that in the standard 8051 the maximum latency is 8 machine cycles which equals 96
machine cycles. This is a 50% reduction in terms of clock periods.
13.5 Interrupt Inputs
Since the external interrupt pins are sampled once each machine cycle, an input high or low should
hold for at least 6 CPU Clocks to ensure proper sampling. If the external interrupt is high for at least
one machine cycle, and then hold it low for at least one machine cycle. This is to ensure that the
transition is seen and that interrupt request flag Ien is set. Ien is automatically cleared by the CPU
when the service routine is called.
If the external interrupt is level-activated, the external source must hold the request active until the
requested interrupt is actually generated. If the external interrupt is still asserted when the interrupt
service routine is completed another interrupt will be generated. It is not necessary to clear the
interrupt flag Ien when the interrupt is level sensitive, it simply tracks the input pin level.
If an external interrupt is enabled when the W78E516D/W78E058D is put into Power Down or Idle
mode, the interrupt will cause the processor to wake up and resume operation. Refer to the section on
Power Reduction Modes for details.
Publication Release Date: July 30, 2008
- 51 -
Revision A01

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