W78E516DPG Nuvoton Technology Corporation of America, W78E516DPG Datasheet - Page 62

• Manufacturer Part Number: W78E516DPG
• Description: IC MCU 8-BIT 64K FLASH 44-PLCC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E516DPG

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

description is shown in the figure below. The frame consists of one start bit (0), 8 data bits (LSB first),
a programmable 9th bit (TB8) and a stop bit (0). The 9th bit received is put into RB8. The baud rate is
programmable to 1/32 or 1/64 of the oscillator frequency, which is determined by the SMOD bit in
PCON SFR. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at
S6P2 following the first roll-over of the divide by 16 counter. The next bit is placed on TxD pin at S6P2
following the next rollover of the divide by 16 counter. Thus the transmission is synchronized to the
divide by 16 counters, and not directly to the write to SBUF signal. After all 9 bits of data are
transmitted, the stop bit is transmitted. The TI flag is set in the S6P2 state after the stop bit has been
put out on TxD pin. This will be at the 11th rollover of the divide by 16 counters after a write to SBUF.
Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data,
with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD
line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the
divide by 16 counters is immediately reset. This helps to align the bit boundaries with the rollovers of
the divide by 16 counters. The 16 states of the counter effectively divide the bit time into 16 slices. The
bit detection is done on a best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and
10th counter states. By using a majority 2 of 3 voting system, the bit value is selected. This is done to
improve the noise rejection feature of the serial port.
If the first bit detected after the falling edge of RxD pin, is not 0, then this indicates an invalid start bit,
and the reception is immediately aborted. The serial port again looks for a falling edge in the RxD line.
If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF.
After shifting in 9 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded
and RI is set. However certain conditions must be met before the loading and setting of RI can be
SMOD
Fosc/2
1/2
RXD
SAMPLE
0
DETECTOR
1
1-To-0
1/16
1/16
TX START
RX CLOCK
Write to
TX START
TX CLOCK
Preliminary W78E516D/W78E058D Data Sheet
SBUF
DETECTOR
BIT
Controllor
Figure 16- 3 Serial port mode 2
Serial
LOAD SBUF
Data Bus
Internal
RX SHIFT
TX SHIFT
TB8
- 62 -
TI
RI
Receive Shift Register
1
0
Transmit Shift Register
CLOCK
SIN
STOP
D8
START
PARIN
CLOCK
LOAD
PAROUT
D8
SOUT
Serial Interrupt
SBUF
RB8
TXD
Read SBUF
Data Bus
Internal