W78E516DPG Nuvoton Technology Corporation of America, W78E516DPG Datasheet - Page 57

• Manufacturer Part Number: W78E516DPG
• Description: IC MCU 8-BIT 64K FLASH 44-PLCC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E516DPG

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

15 WATCHDOG TIMER
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electro-
magnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values
depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software
should restart the Watchdog timer to put it into a known state. The control bits that support the
Watchdog timer are discussed below.
ENW : Enable watchdog if set.
CLRW : Clear watchdog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watchdog is disabled
PS2, PS1, PS0: Watchdog prescaler timer select. Prescaler is selected when set PS2−0 as follows:
The time-out period is obtained using the following equation:
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
OSC
1
×
2
under IDLE mode. Default is cleared.
14
×
PRESCALER 1000 12 mS
PS2 PS1 PS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
×
Preliminary W78E516D/ W78E058D Data Sheet
0
1
0
1
0
1
0
1
×
2
4
8
16
32
64
128
256
Prescaler select
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Publication Release Date: July 30, 2008
Revision A01