ST62T65CB6 STMicroelectronics, ST62T65CB6 Datasheet



Manufacturer Part Number

Specifications of ST62T65CB6

Core Processor
Core Size
Number Of I /o
Program Memory Size
3.8KB (3.8K x 8)
Program Memory Type
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Data Converters
A/D 13x8b
Oscillator Type
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
Number Of Timers
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Development Tools By Supplier
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
March 2009
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
– 8-bit Timer/Counter with 7-bit programmable
3.0 to 6.0V supply operating range
8 MHz maximum clock frequency
-40 to +125°C operating temperature range
Run, Wait and Stop modes
5 interrupt vectors
Look-up table capability in program memory
Data storage in program memory:
user selectable size
Data RAM: 128 bytes
Data EEPROM: 128 bytes (not in ST6255C)
User programmable options
21 I/O pins, fully programmable as:
8 I/O lines can sink up to 30 mA to drive LEDs or
TRIACs directly
8-bit Auto-reload timer with 7-bit programmable
prescaler (AR Timer)
Digital watchdog
Oscillator safe guard (not in ST6265B ROM
Low voltage detector for safe reset (not in
ST6265B ROM devices)
8-bit A/D converter with 13 analog inputs
8-bit synchronous peripheral interface (SPI)
On-chip clock oscillator can be driven by quartz
crystal, ceramic resonator or RC network
User configurable power-on reset
One external non-maskable interrupt
ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
safe reset, auto-reload timer, EEPROM and SPI
Rev 3
Table 1. Device summary
(See end of Datasheet for Ordering Information)
ST6255C ST6265C
8-bit MCUs with ADC,
program memory

Related parts for ST62T65CB6

ST62T65CB6 Summary of contents

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EEPROM and SPI Features 3.0 to 6.0V supply operating range ■ 8 MHz maximum clock frequency ■ -40 to +125°C operating temperature range ■ Run, Wait and Stop modes ■ 5 interrupt vectors ■ Look-up table ...

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ST6255C ST6265C ST6265B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6255C, and ST6265C devices are low cost members of the ST62xx 8-bit HCMOS family of mi- crocontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building ...

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ST6255C ST6265C ST6265B 1.2 PIN DESCRIPTIONS V and V . Power is supplied to the MCU via DD SS these two pins the power connection and the ground connection. SS OSCin and OSCout. These pins ...

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MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Figure 3. Memory Addressing Diagram PROGRAM SPACE 0000h ...

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... U.V. erasure that also results into the whole EPROM context erasure. Note: Once the Readout Protection is activated longer possible, even for STMicroelectronics, to gain access to the OTP contents. Returned parts with a protection set can therefore not be ac- cepted. ...

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MEMORY MAP (Cont’d) 1.3.3 Data Space Data Space accommodates all the data necessary for processing the user program. This space com- prises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and ...

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ST6255C ST6265C ST6265B MEMORY MAP (Cont’d) 1.3.5 Data Window Register (DWR) The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes locat- ed anywhere in program ...

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MEMORY MAP (Cont’d) 1.3.6 Data RAM/EEPROM (DRBR) Address: E8h — Write only 7 DRBR - - - - 4 Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page 2. Bit ...

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ST6255C ST6265C ST6265B MEMORY MAP (Cont’d) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged ...

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MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in write mode, ...

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ST6255C ST6265C ST6265B ROM when E2ENA is low is meaningless and will not trigger a write cycle. 1.4 PROGRAMMING MODES 1.4.1 Option Bytes The two Option Bytes allow configuration capabili the MCUs. Option byte’s content is automati- cally ...

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PROGRAMMING MODES (Cont’d) 1.4.2 EPROM Erasing The EPROM of the windowed package of the MCUs may be erased by exposure to Ultra Violet light. The erasure characteristic of the MCUs is such that erasure begins when the memory is ex- ...

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ST6255C ST6265C ST6265B 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory ...

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ST6255C ST6265C ST6265B CPU REGISTERS (Cont’d) However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register. The PC value is incremented after reading the ...

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CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ble ceramic ...

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ST6255C ST6265C ST6265B CLOCK SYSTEM (Cont’d) Turning on the main oscillator is achieved by re- setting the OSCOFF bit of the A/D Converter Con- trol Register or by resetting the MCU. Restarting the main oscillator implies a delay comprising the ...

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CLOCK SYSTEM (Cont’d) Figure 9. OSG Filtering Principle (1) (2) (3) (4) (1) Maximum Frequency for the device to work correctly (2) Actual Quartz Crystal Frequency at OSCin pin (3) Noise from OSCin (4) Resulting Internal Frequency Figure 10. OSG ...

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ST6255C ST6265C ST6265B CLOCK SYSTEM (Cont’d) Oscillator Control Registers Address: DCh — Write only Reset State: 00h 7 OSCR - - - - 3 Bit 7-4. These bits are not used. Bit 3. Reserved. Cleared at Reset. Must be kept ...

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CLOCK SYSTEM (Cont’d) Figure 11. Clock Circuit Block Diagram MAIN OSCILLATOR Figure 12. Maximum Operating Frequency (f Maximum FREQUENCY (MHz 2.5 3 Notes this area, operation is guaranteed at the ...

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ST6255C ST6265C ST6265B 3.1.4 RESETS The MCU can be reset in four ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. – by Low Voltage Detection (LVD) ...

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RESETS (Cont’d) 3.1.7 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. ...

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ST6255C ST6265C ST6265B RESETS (Cont’d) 3.1.10 MCU Initialization Sequence When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (locat program ROM starting at address 0FFEh). A jump to ...

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RESETS (Cont’d) Table 5. Register Reset Status Register Oscillator Control Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control AR TIMER Mode Control Register AR TIMER Status/Control 0 Register AR TIMER ...

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ST6255C ST6265C ST6265B 3.2 DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can ...

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DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.2.1 Digital Watchdog Register This register is set to 0FEh on Reset: bit ...

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ST6255C ST6265C ST6265B DIGITAL WATCHDOG (Cont’d) 3.2.1 Digital Watchdog Register (DWDR) Address: 0D8h — Read/Write Reset status: 1111 1110b Bit Watchdog Control bit If the hardware option is selected, this bit ...

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DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of 28 instructions ...

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ST6255C ST6265C ST6265B 3.3 INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is asso- ciated with a specific Interrupt Vector which con- tains a Jump instruction ...

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INTERRUPTS (Cont’d) 3.3.2 Interrupt Procedure The interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context ...

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ST6255C ST6265C ST6265B INTERRUPTS (Cont’d) 3.3.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and ...

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ST6255C ST6265C ST6265B 3.4 POWER SAVING MODES The WAIT and STOP modes have been imple- mented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described ...

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POWER SAVING MODE (Cont’d) 3.4.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be noted that the restart sequence ...

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ST6255C ST6265C ST6265B 4 ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: – Input without pull-up or interrupt – Input with pull-up and interrupt ...

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I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option reg- isters (OR). Table ...

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ST6255C ST6265C ST6265B I/O PORTS (Cont’d) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recom- mended safe ...

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I/O PORTS (Cont’d) Table 11. I/O Port Option Selections MODE AVAILABLE ON PA0-PA7 Input PB0-PB5, PB6-PB7 PC0-PC4 PA0-PA7 Input PB0-PB5, PB6-PB7 with pull up PC0-PC4 Input PA0-PA7 with pull up PB0-PB5, PB6-PB7 with interrupt PC0-PC4 PA0-PA7 Analog Input PC0-PC4 Open ...

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ST6255C ST6265C ST6265B I/O PORTS (Cont’d) 4.1.3 Timer 1 Alternate function Option When bit TOUT of register TSCR1 is low, pin PC1/ Timer 1 is configured through the port registers as any standard pin of Port ...

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I/O PORTS (Cont’d) Figure 24. Peripheral Interface Configuration of SPI, Timer 1 and AR Timer PC3/Sout PC2/Sin PC4/SCK PC1/TIM1 ARTIMin ARTIMout V DD PP/OD 1 MUX 0 REGISTER MUX 0 1 MUX 0 DR PP/OD 1 MUX ...

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ST6255C ST6265C ST6265B 4.2 TIMER The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 The peripheral may be configured in three different operating modes. Figure ...

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TIMER (Cont’d) 4.2.1 Timer Operating Modes There are three operating modes, which are se- lected by the TOUT and DOUT bits (see TSCR register). These three modes correspond to the two clocks which can be connected to the 7-bit prescaler ...

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ST6255C ST6265C ST6265B TIMER (Cont’d) 4.2.3 Application Notes The user can select the presence of an on-chip pull-up on the TIMER pin as option. TMZ is set when the counter reaches zero; howev- er, it may also be set by ...

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AUTO-RELOAD TIMER The Auto-Reload Timer (AR Timer) on-chip pe- ripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as f external ...

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AUTO-RELOAD TIMER (Cont’d) It should be noted that the reload values will also affect the value and the resolution of the duty cycle of PWM output signal. To obtain a signal on ARTI- Mout, the contents of the ARCP register ...

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ST6255C ST6265C ST6265B AUTO-RELOAD TIMER (Cont’d) Capture Mode with PWM Generation. In this mode, the AR counter operates as a free running 8-bit counter fed by the prescaler output. The counter is incremented on every clock rising edge. An 8-bit ...

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AUTO-RELOAD TIMER (Cont’d) 4.3.3 AR Timer Registers AR Mode Control Register (ARMC) Address: D5h — Read/Write Reset status: 00h 7 TCLD TEN PWMOE EIE CPIE The AR Mode Control Register ARMC is used to program the different operating modes of ...

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ST6255C ST6265C ST6265B AUTO-RELOAD TIMER (Cont’d) AR Status Control Register 1(ARSC1) Address: D7h — Read/Write 7 PS2 PS1 PS0 D4 SL1 Bist 7-5 = PS2-PS0: Prescaler Division Selection Bits 2-0. These bits determine the Prescaler divi- sion ratio. The prescaler ...

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A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device depend- ent), offering 8-bit resolution with a typical conver- sion time of ...

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ST6255C ST6265C ST6265B A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. Such switching will affect ...

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SERIAL PERIPHERAL INTERFACE (SPI) The SPI peripheral is an optimized synchronous serial interface with programmable transmission modes and master/slave capabilities supporting a wide range of industry standard SPI specifications. The SPI interface may also implement asynchro- nous data transfer, ...

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ST6255C ST6265C ST6265B SERIAL PERIPHERAL INTERFACE SPI (Cont’d) 4.5.1 SPI Registers SPI Mode Control Register (MOD) Address: E2h — Read/Write Reset status: 00h 7 SPRUN SPIE CPHA SPCLK SPIN The MOD register defines and controls the trans- mission modes and ...

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SERIAL PERIPHERAL INTERFACE SPI (Cont’d) SPI DIV Register (DIV) Address: E1h — Read/Write Reset status: 00h 7 SPINT DOV6 DIV5 DIV4 DIV3 The SPIDIV register defines the transmission rate and frame format and contains the interrupt flag. Bits CD0-CD2, DIV3-DIV6 ...

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ST6255C ST6265C ST6265B SERIAL PERIPHERAL INTERFACE SPI (Cont’d) 4.5.2 SPI Timing Diagrams Figure 31. CPOL = 0 Clock Polarity Normal, CPHA = 0 Phase Selection Normal SPRUN SCK Sin Sampling Sout b7 Figure 32. CPOL = 1 Clock Polarity Inverted, ...

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SERIAL PERIPHERAL INTERFACE SPI (Cont’d) Figure 33. CPOL = 0 Clock Polarity Normal, CPHA = 1 Phase Selection Shifted SPRUN SCK Sin Sampling Sout b7 Figure 34. CPOL = 1 Clock Polarity Inverted, CPHA = 1 Phase Selection Shifted SPRUN ...

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ST6255C ST6265C ST6265B 5 SOFTWARE 5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. ...

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INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, ...

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ST6255C ST6265C ST6265B INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instruc- tions one operand is always the accumulator while the other can be either ...

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INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. One group either sets or ...

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ST6255C ST6265C ST6265B Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6 LOW 0 1 0000 0001 HI 2 JRNZ 4 CALL abc 0000 1 pcr 2 ext 1 ...

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Opcode Map Summary (Continued) LOW 8 9 1000 1001 HI 2 JRNZ abc 0000 1 pcr 2 ext 1 2 JRNZ abc 0001 1 pcr 2 ext 1 2 JRNZ ...

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ST6255C ST6265C ST6265B 6 ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage ...

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RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A Operating Supply Voltage (Except ST626xB ROM devices Operating Supply Voltage (ST626xB ROM devices) 2) Oscillator Frequency (Except ST626xB ROM devices) f OSC 2) Oscillator Frequency (ST626xB ROM devices) ...

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ST6255C ST6265C ST6265B 6.3 DC ELECTRICAL CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter V Input Low Level Voltage IL All Input pins V Input High Level Voltage IH All Input pins (1) Hysteresis Voltage V ...

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DC ELECTRICAL CHARACTERISTICS (Cont’ -40 to +85°C unless otherwise specified)) A Symbol Parameter V LVD Threshold in power- LVD threshold in powerdown dn Low Level Output Voltage All Output pins V OL Low Level Output Voltage ...

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ST6255C ST6265C ST6265B 1. Period for which V has to be connected allow internal Reset function at next power-up oscillator frequency above 1MHz is recommended for reliable A/D results. 3. Measure performed with OSCin ...

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Input Frequency on ARTIMin Pin IN Figure 36. Vol versus Iol on all I/O port at Vdd= This curves represents typical variations and is given for guidance only Figure 37. Vol versus ...

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ST6255C ST6265C ST6265B Figure 38. Vol versus Iol for High sink (30mA) I/Oports at T=25° This curves represents typical variations and is given for guidance only Figure 39. Vol versus Iol for ...

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Figure 41. Voh versus Ioh on all I/O port at Vdd= This curves represents typical variations and is given for guidance only Figure 42. Idd WAIT versus V 2.5 2 1.5 1 0.5 ...

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ST6255C ST6265C ST6265B Figure 44. Idd STOP versus V 2 1.5 1 0.5 0 -0.5 3V This curves represents typical variations and is given for guidance only Figure 45. Idd WAIT versus V 2.5 2 1 ...

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Figure 47. LVD thresholds versus temperature 4.2 4.1 4 3.9 3.8 3.7 -40°C This curves represents typical variations and is given for guidance only Figure 48. RC frequency versus This curves represents typical variations and is given ...

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ST6255C ST6265C ST6265B Figure 49. RC frequency versus 0.1 3 This curves represents typical variations and is given for guidance only 74/84 (Except for ST626xB ROM devices) DD 3.5 4 4.5 5 VDD (volts) R=47K R=100K R=470K ...

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PACKAGE MECHANICAL DATA In order to meet environmental requirements, ST offers these devices in different grades of ECO- ® PACK packages, depending on their level of en- vironmental compliance. ECOPACK tions, grade definitions and product status are Figure 50. ...

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ST6255C ST6265C ST6265B Figure 51. 28-Pin Plastic Small Outline Package, 300-mil Width D B 76/ 45× inches Dim. Min Typ Max Min Typ A 2.35 2.65 0.093 A1 0.10 ...

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PACKAGE MECHANICAL DATA (Cont’d) Figure 52. 28-Ceramic Dual In Line Package, 600-mil Width Figure 53. 28-Pin Plastic Shrink Small Outline Package CDIP28W ST6255C ST6265C ST6265B mm inches Dim. Min Typ ...

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... ST62E65CF1 3884 (EPROM) ST62T55CB6 ST62T55CB3 ST62T55CM6 3884 (OTP) ST62T55CM3 ST62T55CN6 ST62T55CN3 ST62T65CB6 ST62T65CB3 ST62T65CM6 3884 (OTP) ST62T65CM3 ST62T65CN6 ST62T65CN3 8.1.1 IMPORTANT NOTE For OTP devices, data retention and programma- bility must be guaranteed by a screening proce- dure. Refer to Application Note AN886. ...

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... MCU. The listing is then returned to the customer who must thoroughly check, com- plete, sign and return it to STMicroelectronics. The signed listing forms a part of the contractual agree- ment for the production of the specific customer MCU ...

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... All unused bytes must be set to FFh. The selected mask options are communicated to STMicroelectronics using the correctly filled OP- TION LIST appended. See 8.3.3 Listing Generation and Verification When STMicroelectronics receives the user’s ROM contents, a computer listing is generated from it ...

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... The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points. Table 28. ROM device ordering Information Order code ROM ST6255CB1/XXX ST6255CB6/XXX ST6255CB3/XXX ST6255CM1/XXX ST6255CM6/XXX ST6255CM3/XXX ST6255CN1/XXX ST6255CN6/XXX ST6255CN3/XXX 3884 Bytes ST6265BB1/XXX ST6265BB6/XXX ST6265BB3/XXX ST6265BM1/XXX ST6265BM6/XXX ST6265BM3/XXX ST6265BN1/XXX ST6265BN6/XXX ST6265BN3/XXX Table 27. ROM Memory Map for ST6255C/65B ...

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... Enabled [ ] Enabled [ ] Enabled FASTROM Enabled ROM Enabled Fuse is blown by STMicroelectronics [ ] Fuse can be blown by the customer [ ] Disabled [ ] Enabled [ ] Enabled [ ] Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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REVISION HISTORY Table 29. Document revision history Date Rev. Modification of “Additional Notes for EEPROM Parallel Mode” (p.13) In section 4.2.4 on page 45: vector #4 instead of vector #3 in description of bit 6 (TSCR regis- ter). Jul-2001 ...

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... ST6255C ST6265C ST6265B Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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