IC MCU 8BIT OTP/EPROM 20 PSOIC

ST62T60CM6

Manufacturer Part NumberST62T60CM6
DescriptionIC MCU 8BIT OTP/EPROM 20 PSOIC
ManufacturerSTMicroelectronics
SeriesST6
ST62T60CM6 datasheet
 


Specifications of ST62T60CM6

Core ProcessorST6Core Size8-Bit
Speed8MHzConnectivitySPI
PeripheralsLED, LVD, POR, WDTNumber Of I /o13
Program Memory Size3.8KB (3.8K x 8)Program Memory TypeOTP
Eeprom Size128 x 8Ram Size128 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 7x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-SOIC (7.5mm Width)Processor SeriesST62T6x
CoreST6Data Bus Width8 bit
Data Ram Size128 BInterface TypeSPI
Maximum Clock Frequency8 MHzNumber Of Programmable I/os13
Number Of Timers2Operating Supply Voltage3 V to 6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
Development Tools By SupplierST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-IIMinimum Operating Temperature- 40 C
On-chip Adc8 bitLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names497-2102-5  
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Page 1/83

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safe reset, auto-reload timer, EEPROM and SPI
Features
3.0 to 6.0 V Supply Operating Range
8 MHz Maximum Clock Frequency
-40 to +125°C Operating Temperature Range
Run, Wait and Stop Modes
5 Interrupt Vectors
Look-up Table capability in Program Memory
Data Storage in Program Memory:
User selectable size
Data RAM: 128 bytes
Data EEPROM: 64/128 bytes (not in ST6253C
devices)
User Programmable Options
13 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
6 I/O lines can sink up to 30 mA to drive LEDs or
TRIACs directly
8-bit Timer / Counter with 7-bit programmable
prescaler
8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
Digital Watchdog
Oscillator Safe Guard (not in ROM devices)
Low Voltage Detector for Safe Reset (not in
ROM devices)
8-bit A/D Converter with 7 analog inputs
8-bit Synchronous Peripheral Interface (SPI)
On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
User configurable Power-on Reset
One external Non-Maskable Interrupt
ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
March 2009
ST6253C ST6263C ST6263B
ST6260C ST6260B
8-bit MCUs with A/D converter,
(See end of Datasheet for Ordering Information)
DEVICE SUMMARY
DEVICE
ST6253C
ST6260C / ST6260B
ST6263C / ST6263B
Rev. 3
PDIP20
PSO20
CDIP20W
Program memory
EEPROM
(Bytes)
(Bytes)
1836
-
3884
128
1836
64
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ST62T60CM6 Summary of contents

  • Page 1

    EEPROM and SPI Features 3.0 to 6.0 V Supply Operating Range ■ 8 MHz Maximum Clock Frequency ■ -40 to +125°C Operating Temperature Range ■ Run, Wait and Stop Modes ■ 5 Interrupt Vectors ■ Look-up ...

  • Page 2

    ST6253C ST6263C ST6263B ST6260C ST6260B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62T53C, ST62T60C, ST62T63C and ST62E60C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity ap- plications. All ST62xx devices are based on ...

  • Page 5

    ST6253C ST6263C ST6263B ST6260C ST6260B 1.2 PIN DESCRIPTIONS V and V . Power is supplied to the MCU via DD SS these two pins the power connection and the ground connection. SS OSCin and OSCout. ...

  • Page 6

    MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Figure 3Memory Addressing Diagram PROGRAM SPACE 0000h PROGRAM ...

  • Page 7

    ... U.V. erasure that also results into the whole EPROM context erasure. Note: Once the Readout Protection is activated longer possible, even for STMicroelectronics, to gain access to the OTP contents. Returned parts with a protection set can therefore not be ac- cepted. ...

  • Page 8

    MEMORY MAP (Cont’d) 1.3.3 Data Space Data Space accommodates all the data necessary for processing the user program. This space com- prises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and ...

  • Page 9

    ST6253C ST6263C ST6263B ST6260C ST6260B MEMORY MAP (Cont’d) 1.3.5 Data Window Register (DWR) The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes locat- ed anywhere ...

  • Page 10

    MEMORY MAP (Cont’d) 1.3.6 Data RAM/EEPROM (DRBR) Address: E8h — Write only 7 DRBR - - - - 4 Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page 2. Bit ...

  • Page 11

    ST6253C ST6263C ST6263B ST6260C ST6260B MEMORY MAP (Cont’d) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh ...

  • Page 12

    MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in write mode, ...

  • Page 13

    ST6253C ST6263C ST6263B ST6260C ST6260B 1.4 PROGRAMMING MODES 1.4.1 Option Bytes The two Option Bytes allow configuration capabili the MCUs. Option byte’s content is automati- cally read, and the selected options enabled, when the chip reset is activated. ...

  • Page 14

    PROGRAMMING MODES (Cont’d) 1.4.2 EPROM Erasing The EPROM of the windowed package of the MCUs may be erased by exposure to Ultra Violet light. The erasure characteristic of the MCUs is such that erasure begins when the memory is ex- ...

  • Page 15

    ST6253C ST6263C ST6263B ST6260C ST6260B 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip ...

  • Page 16

    CPU REGISTERS (Cont’d) However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register. The PC value is incremented after reading the ad- dress of ...

  • Page 17

    ST6253C ST6263C ST6263B ST6260C ST6260B 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal ...

  • Page 18

    CLOCK SYSTEM (Cont’d) Turning on the main oscillator is achieved by re- setting the OSCOFF bit of the A/D Converter Con- trol Register or by resetting the MCU. Restarting the main oscillator implies a delay comprising the oscillator start up ...

  • Page 19

    ST6253C ST6263C ST6263B ST6260C ST6260B CLOCK SYSTEM (Cont’d) Figure 10. OSG Filtering Principle (1) (2) (3) (4) (1) Maximum Frequency for the device to work correctly (2) Actual Quartz Crystal Frequency at OSCin pin (3) Noise from OSCin (4) Resulting ...

  • Page 20

    CLOCK SYSTEM (Cont’d) Oscillator Control Registers Address: DCh — Write only Reset State: 00h 7 OSCR - - - - 3 Bit 7-4. These bits are not used. Bit 3. Reserved. Cleared at Reset. Must be kept cleared. Bit 2. ...

  • Page 21

    ST6253C ST6263C ST6263B ST6260C ST6260B CLOCK SYSTEM (Cont’d) Figure 12. Clock Circuit Block Diagram MAIN OSCILLATOR Figure 13. Maximum Operating Frequency (f Maximum FREQUENCY (MHz 2.5 Notes this area, operation ...

  • Page 22

    RESETS The MCU can be reset in four ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. – by Low Voltage Detection (LVD) 3.2.1 RESET Input ...

  • Page 23

    ST6253C ST6263C ST6263B ST6260C ST6260B RESETS (Cont’d) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the ...

  • Page 24

    RESETS (Cont’d) 3.2.6 MCU Initialization Sequence When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (locat program ROM starting at address 0FFEh). A jump to the beginning of ...

  • Page 25

    ST6253C ST6263C ST6263B ST6260C ST6260B RESETS (Cont’d) Table 5Register Reset Status Register Oscillator Control Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control AR TIMER Mode Control Register AR TIMER Status/Control ...

  • Page 26

    DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset ...

  • Page 27

    ST6253C ST6263C ST6263B ST6260C ST6260B DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register This register is set ...

  • Page 28

    DIGITAL WATCHDOG (Cont’d) 3.3.1 Digital Watchdog Register (DWDR) Address: 0D8h — Read/Write Reset status: 1111 1110 Bit Watchdog Control bit If the hardware option is selected, this bit is forced ...

  • Page 29

    ST6253C ST6263C ST6263B ST6260C ST6260B DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, ...

  • Page 30

    INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is asso- ciated with a specific Interrupt Vector which con- tains a Jump instruction to the associated ...

  • Page 31

    ST6253C ST6263C ST6263B ST6260C ST6260B INTERRUPTS (Cont’d) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the ...

  • Page 32

    INTERRUPTS (Cont’d) 3.4.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed ...

  • Page 33

    ST6253C ST6263C ST6263B ST6260C ST6260B INTERRUPTS (Cont’d) Figure 22. Interrupt Block Diagram FROM REGISTER PORT A,B,C SINGLE BIT ENABLE PBE V DD PORT A PBE PORT B Bits PORT C PBE Bits SPIDIV Register SPINT bit SPIE bit SPIMOD Register ...

  • Page 34

    POWER SAVING MODES The WAIT and STOP modes have been imple- mented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in the following ...

  • Page 35

    ST6253C ST6263C ST6263B ST6260C ST6260B POWER SAVING MODE (Cont’d) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be ...

  • Page 36

    ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: – Input without pull-up or interrupt – Input with pull-up and interrupt – Input with ...

  • Page 37

    ST6253C ST6263C ST6263B ST6260C ST6260B I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and ...

  • Page 38

    I/O PORTS (Cont’d) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recom- mended safe transitions are illustrated ...

  • Page 39

    ST6253C ST6263C ST6263B ST6260C ST6260B I/O PORTS (Cont’d) Table 11I/O Port Option Selections MODE AVAILABLE ON PA0-PA3 Input PB0-PB3, PB6-PB7 PC2-PC4 PA0-PA3 Input PB0-PB3, PB6-PB7 with pull up PC2-PC4 Input PA0-PA3 with pull up PB0-PB3, PB6-PB7 PC2-PC4 with interrupt PA0-PA3 ...

  • Page 40

    I/O PORTS (Cont’d) 4.1.3 AR Timer Alternate function Option When bit PWMOE of register ARMC is low, pin AR- TIMout/PB7 is configured as any standard pin of port B through the port registers. When PWMOE is high, ARTIMout/PB7 is the ...

  • Page 41

    ST6253C ST6263C ST6263B ST6260C ST6260B I/O PORTS (Cont’d) Figure 25Peripheral Interface Configuration of SPI, Timer 1 and AR Timer PC3/Sout PC2/Sin PC4/SCK PC1/TIM1 ARTIMin ARTIMout 41/ PP/OD 1 MUX 0 REGISTER MUX 0 1 MUX ...

  • Page 42

    TIMER The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 Figure 26 shows the Timer Block Diagram. The content of the 8-bit counter can ...

  • Page 43

    ST6253C ST6263C ST6263B ST6260C ST6260B TIMER (Cont’d) 4.2.1 Timer Operation The Timer prescaler is clocked by the prescaler clock input (f ÷ 12). INT The user can select the desired prescaler division ratio through the PS2, PS1, PS0 bits. When ...

  • Page 44

    TIMER (Cont’d) A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i. write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the TMZ bit ...

  • Page 45

    ST6253C ST6263C ST6263B ST6260C ST6260B 4.3 AUTO-RELOAD TIMER The Auto-Reload Timer (AR Timer) on-chip pe- ripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to ...

  • Page 46

    AUTO-RELOAD TIMER (Cont’d) Figure 28. AR Timer Block Diagram f INT INT U AR PRESCALER X PS0-PS2 CC0-CC1 PB6/ ARTIMin SL0-SL1 EF SYNCHRO ST6253C ST6263C ST6263B ST6260C ST6260B DATA BUS 8 AR COMPARE REGISTER 8 COMPARE 8 ...

  • Page 47

    ST6253C ST6263C ST6263B ST6260C ST6260B AUTO-RELOAD TIMER (Cont’d) It should be noted that the reload values will also affect the value and the resolution of the duty cycle of PWM output signal. To obtain a signal on ARTI- Mout, the ...

  • Page 48

    AUTO-RELOAD TIMER (Cont’d) Capture Mode with PWM Generation. In this mode, the AR counter operates as a free running 8-bit counter fed by the prescaler output. The counter is incremented on every clock rising edge. An 8-bit capture operation from ...

  • Page 49

    ST6253C ST6263C ST6263B ST6260C ST6260B AUTO-RELOAD TIMER (Cont’d) 4.3.3 AR Timer Registers AR Mode Control Register (ARMC) Address: D5h — Read/Write Reset status: 00h 7 TCLD TEN PWMOE EIE CPIE The AR Mode Control Register ARMC is used to program ...

  • Page 50

    AUTO-RELOAD TIMER (Cont’d) AR Status Control Register 1(ARSC1) Address: D7h — Read/Write 7 PS2 PS1 PS0 D4 SL1 Bist 7-5 = PS2-PS0: Prescaler Division Selection Bits 2-0. These bits determine the Prescaler divi- sion ratio. The prescaler itself is not ...

  • Page 51

    ST6253C ST6263C ST6263B ST6260C ST6260B 4.4 A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device depend- ent), offering 8-bit resolution with a ...

  • Page 52

    A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. Such switching will affect the sup- ply ...

  • Page 53

    ST6253C ST6263C ST6263B ST6260C ST6260B 4.5 SERIAL PERIPHERAL INTERFACE (SPI) The SPI peripheral is an optimized synchronous serial interface with programmable transmission modes and master/slave capabilities supporting a wide range of industry standard SPI specifications. The SPI interface may also ...

  • Page 54

    SERIAL PERIPHERAL INTERFACE SPI (Cont’d) 4.5.1 SPI Registers SPI Mode Control Register (MOD) Address: E2h — Read/Write Reset status: 00h 7 SPRUN SPIE CPHA SPCLK SPIN The MOD register defines and controls the trans- mission modes and characteristics. This register ...

  • Page 55

    ST6253C ST6263C ST6263B ST6260C ST6260B SERIAL PERIPHERAL INTERFACE SPI (Cont’d) SPI DIV Register (DIV) Address: E1h — Read/Write Reset status: 00h 7 SPINT DOV6 DIV5 DIV4 DIV3 The SPIDIV register defines the transmission rate and frame format and contains the ...

  • Page 56

    SERIAL PERIPHERAL INTERFACE SPI (Cont’d) 4.6 SPI Timing Diagrams Figure 32. CPOL = 0 Clock Polarity Normal, CPHA = 0 Phase Selection Normal SPRUN SCK Sin Sampling Sout b7 Figure 33. CPOL = 1 Clock Polarity Inverted, CPHA = 0 ...

  • Page 57

    ST6253C ST6263C ST6263B ST6260C ST6260B SERIAL PERIPHERAL INTERFACE SPI (Cont’d) Figure 34. CPOL = 0 Clock Polarity Normal, CPHA = 1 Phase Selection Shifted SPRUN SCK Sin Sampling Sout b7 Figure 35. CPOL = 1 Clock Polarity Inverted, CPHA = ...

  • Page 58

    SOFTWARE 5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core ...

  • Page 59

    ST6253C ST6263C ST6263B ST6260C ST6260B 5.3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- ...

  • Page 60

    INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instruc- tions one operand is always the accumulator while the other can be either a data space ...

  • Page 61

    ST6253C ST6263C ST6263B ST6260C ST6260B INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. ...

  • Page 62

    Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6 LOW 0 1 0000 0001 HI 2 JRNZ 4 CALL abc 0000 1 pcr 2 ext 1 2 JRNZ 4 ...

  • Page 63

    ST6253C ST6263C ST6263B ST6260C ST6260B Opcode Map Summary (Continued) LOW 8 9 1000 1001 HI 2 JRNZ abc 0000 1 pcr 2 ext 1 2 JRNZ abc 0001 1 pcr ...

  • Page 64

    ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the ...

  • Page 65

    ST6253C ST6263C ST6263B ST6260C ST6260B 6.2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A Operating Supply Voltage (Except ST626xB ROM devices Operating Supply Voltage (ST626xB ROM devices) 2) Oscillator Frequency (Except ST626xB ROM devices) f OSC 2) ...

  • Page 66

    DC ELECTRICAL CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter V Input Low Level Voltage IL All Input pins V Input High Level Voltage IH All Input pins (1) Hysteresis Voltage V Hys All Input ...

  • Page 67

    ST6253C ST6263C ST6263B ST6260C ST6260B DC ELECTRICAL CHARACTERISTICS (Cont’ -40 to +85°C unless otherwise specified)) A Symbol Parameter V LVD Threshold in power- LVD threshold in powerdown dn Low Level Output Voltage All Output pins V ...

  • Page 68

    A/D CONVERTER CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter Res Resolution (1) (2) A Total Accuracy TOT t Conversion Time C ZIR Zero Input Reading FSR Full Scale Reading Analog Input Current During AD ...

  • Page 69

    ST6253C ST6263C ST6263B ST6260C ST6260B Figure 37. Vol versus Iol on all I/O port at Vdd= This curves represents typical variations and is given for guidance only Figure 38. Vol versus Iol on ...

  • Page 70

    Figure 40. Vol versus Iol for High sink (30mA) I/O ports at Vdd= This curves represents typical variations and is given for guidance only Figure 41. Voh versus Ioh on all I/O ...

  • Page 71

    ST6253C ST6263C ST6263B ST6260C ST6260B Figure 43. Idd WAIT versus V 2.5 2 1 This curves represents typical variations and is given for guidance only Figure 44. Idd STOP versus ...

  • Page 72

    Figure 46. Idd WAIT versus V 2.5 2 1 This curves represents typical variations and is given for guidance only Figure 47. Idd RUN versus This curves represents typical ...

  • Page 73

    ST6253C ST6263C ST6263B ST6260C ST6260B Figure 49. RC frequency versus This curves represents typical variations and is given for guidance only Figure 50. RC frequency versus 0.1 3 This curves represents typical variations and ...

  • Page 74

    PACKAGE MECHANICAL DATA In order to meet environmental requirements, ST offers these devices in different grades of ECO- ® PACK packages, depending on their level of en- vironmental compliance. ECOPACK tions, grade definitions and product status are Figure 51. ...

  • Page 75

    ST6253C ST6263C ST6263B ST6260C ST6260B PACKAGE MECHANICAL DATA (Cont’d) Figure 53. 20-Pin Plastic Small Outline Package, 300-mil Width 75/ 45× inches Dim. Min Typ Max Min Typ A ...

  • Page 76

    ... Sales Type Memory (Bytes) ST62T53CB6 ST62T53CB3 1836 (OTP) ST62T53CM6 ST62T53CM3 ST62T60CB6 ST62T60CB3 3884 (OTP) ST62T60CM6 ST62T60CM3 ST62T63CB6 1836 (OTP) ST62T63CM6 ST62E60CF1 3884 (EPROM) 8.1.1 IMPORTANT NOTE For OTP devices, data retention and programma- bility must be guaranteed by a screening proce- dure. Refer to Application Note AN886. ...

  • Page 77

    ... ST62P63CM3/XXX (*) Advanced information (*) 77/83 the customer who must thoroughly check, com- plete, sign and return it to STMicroelectronics. The signed listing forms a part of the contractual agree- ment for the production of the specific customer MCU. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points ...

  • Page 78

    ROM VERSIONS Table 1. ROM Version Ordering Information Sales Type ROM (Bytes) ST6253CB1/XXX ST6253CB6/XXX ST6253CB3/XXX ST6253CM1/XXX ST6253CM6/XXX ST6253CM3/XXX ST6260BB1/XXX ST6260BB6/XXX ST6260BB3/XXX ST6260BM1/XXX ST6260BM6/XXX ST6260BM3/XXX ST6263BB1/XXX ST6263BB6/XXX ST6263BB3/XXX ST6263BM1/XXX ST6263BM6/XXX ST6263BM3/XXX The ST6253C, ST6260B and ST6263B are mask programmed ROM ...

  • Page 79

    ... STMicroelec- tronics. The signed listing forms a part of the con- tractual agreement for the creation of the specific customer mask. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points. 5V 47mF ...

  • Page 80

    Table 27. ROM Memory Map for ST6260B Device Address 0000h-007Fh 0080h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh NMI Interrupt Vector 0FFEh-0FFFh ST6253C ST6263C ST6263B ST6260C ST6260B Table 28. ROM Memory Map for ST6253C/63B Description Reserved User ROM Reserved Interrupt Vectors Reserved Reset ...

  • Page 81

    ... Enabled [ ] Enabled [ ] Enabled FASTROM Enabled ROM Enabled Fuse is blown by STMicroelectronics [ ] Fuse can be blown by the customer [ ] Disabled [ ] Enabled [ ] Enabled [ ] Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 82

    REVISION HISTORY Table 29. Document revision history Date Rev. Modification of “Additional Notes for EEPROM Parallel Mode” (p.13) In section 4.2 on page 43: vector #4 instead of vector #3 for the timer interrupt request. Jul-2001 2.8 Changed f ...

  • Page 83

    ... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...