MC908QY2AMDTE Freescale Semiconductor, MC908QY2AMDTE Datasheet - Page 112

• Manufacturer Part Number: MC908QY2AMDTE
• Description: IC MCU 8BIT 1.5K FLASH 16TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QY2AMDTE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Processor Series: HC08QY
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
13.4.2 Active Resets from Internal Sources
The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the
CONFIG2 register enables the pin for the reset function. This section assumes the RSTEN bit is set when
describing activity on the RST pin.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
All internal reset sources actively pull the RST pin low for 32 BUSCLKX4 cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
(see
LVI, or POR (see
112
Figure
13-4). An internal reset can be caused by an illegal address, illegal opcode, COP time out,
BUSCLKX4
ADDRESS
For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles.
The internal reset signal then follows the sequence from the falling edge of
RST shown in
The COP reset is asynchronous to the bus clock.
IRST
RST
BUS
Figure
Reset Recovery Type
13-5).
Figure
All others
POR/LVI
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
Figure 13-5. Sources of Internal Reset
ILLEGAL ADDRESS RST
RST PULLED LOW BY MCU
ILLEGAL OPCODE RST
Table 13-2. Reset Recovery Timing
Figure 13-4. Internal Reset Timing
13-4.
COPRST
32 CYCLES
POR
LVI
NOTE
Actual Number of Cycles
4163 (4096 + 64 + 3)
INTERNAL RESET
32 CYCLES
67 (64 + 3)
VECTOR HIGH
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