MC908QY2AMDTE Freescale Semiconductor, MC908QY2AMDTE Datasheet - Page 24

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MC908QY2AMDTE

Manufacturer Part Number
MC908QY2AMDTE
Description
IC MCU 8BIT 1.5K FLASH 16TSSOP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908QY2AMDTE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-TSSOP
Processor Series
HC08QY
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
Memory
24
$001D
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
Addr.
TIM Counter Register High
TIM Counter Register Low
TIM Channel 0 Status and
Configuration Register 2
Configuration Register 1
Control Register (TSC0)
Register High (TMODH)
IRQ Status and Control
Register High (TCH0H)
TIM Status and Control
Register Low (TMODL)
Register Low (TCH0L)
Register Name
TIM Counter Modulo
TIM Counter Modulo
Register (INTSCR)
Register (TSC)
TIM Channel 0
TIM Channel 0
See page 132.
See page 134.
See page 134.
See page 134.
See page 134.
See page 135.
See page 137.
See page 137.
(CONFIG2)
(CONFIG1)
See page 81.
See page 57.
See page 58.
(TCNTH)
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5)
(TCNTL)
(1)
(1)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
1. One-time writable register after each reset.
2. RSTEN reset to 0 by a power-on reset (POR) only.
1. One-time writable register after each reset.
2. LVITRIP reset to 0 by a power-on reset (POR) only.
IRQPUD
COPRS
CH0F
Bit 15
Bit 15
Bit 15
Bit 7
TOF
Bit 7
Bit 7
Bit 7
0
0
0
0
0
0
0
0
1
1
0
0
= Unimplemented
LVISTOP
IRQEN
CH0IE
Bit 14
Bit 14
Bit 14
TOIE
Bit 6
Bit 6
Bit 6
6
0
0
0
0
0
0
0
1
1
0
LVIRSTD
TSTOP
MS0B
Bit 13
Bit 13
Bit 13
Bit 5
Bit 5
Bit 5
R
5
0
0
0
0
1
0
0
1
1
0
Indeterminate after reset
Indeterminate after reset
LVIPWRD
MS0A
TRST
Bit 12
Bit 12
Bit 12
Bit 4
Bit 4
Bit 4
R
R
4
0
0
0
0
0
0
0
0
1
1
0
= Reserved
LVITRIP
ELS0B
Bit 11
Bit 11
Bit 11
IRQF
Bit 3
Bit 3
Bit 3
0
R
3
0
0
0
0
0
0
1
1
0
(2)
SSREC
ELS0A
Bit 10
Bit 10
Bit 10
U = Unaffected
ACK
Bit 2
Bit 2
Bit 2
PS2
R
2
0
0
0
0
0
0
0
1
1
0
Freescale Semiconductor
OSCENIN-
IMASK
STOP
STOP
TOV0
PS1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
1
0
0
0
0
0
0
1
1
0
CH0MAX
RSTEN
MODE
COPD
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
PS0
0
0
0
0
0
0
1
1
0
(2)

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