MC908QY2AMDTE Freescale Semiconductor, MC908QY2AMDTE Datasheet - Page 137

• Manufacturer Part Number: MC908QY2AMDTE
• Description: IC MCU 8BIT 1.5K FLASH 16TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QY2AMDTE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Processor Series: HC08QY
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

TOVx — Toggle-On-Overflow Bit
CHxMAX — Channel x Maximum Duty Cycle Bit
14.8.5 TIM Channel Registers
These read/write registers contain the captured counter value of the input capture function or the output
compare value of the output compare function. The state of the TIM channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Freescale Semiconductor
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the counter overflows. When channel x is an input capture channel, TOVx has no effect.
When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
Reset:
Reset:
Read:
Write:
Read:
Write:
When TOVx is set, a counter overflow takes precedence over a channel x
output compare if both occur at the same time.
CHxMAX
T1CHx
OVERFLOW
Bit 15
Bit 7
Bit 7
Bit 7
Figure 14-12. TIM Channel x Register High (TCHxH)
Figure 14-13. TIM Channel Register Low (TCHxL)
Figure 14-11
COMPARE
PERIOD
OUTPUT
Bit 14
Bit 6
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
6
6
Figure 14-11. CHxMAX Latency
OVERFLOW
Bit 13
Bit 5
5
5
shows, the CHxMAX bit takes effect in the cycle after it is set
COMPARE
OUTPUT
Indeterminate after reset
Indeterminate after reset
Bit 12
NOTE
Bit 4
4
4
OVERFLOW
Bit 11
Bit 3
COMPARE
3
3
OUTPUT
OVERFLOW
Bit 10
Bit 2
2
2
COMPARE
OUTPUT
Bit 9
Bit 1
1
1
OVERFLOW
Bit 0
Bit 8
Bit 0
Bit 0
Registers
137