MC908QY2AMDTE Freescale Semiconductor, MC908QY2AMDTE Datasheet - Page 143

• Manufacturer Part Number: MC908QY2AMDTE
• Description: IC MCU 8BIT 1.5K FLASH 16TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QY2AMDTE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Processor Series: HC08QY
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

15.2.2.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the
MCU is in a state of break interrupt with monitor mode.
BDCOP — Break Disable COP Bit
15.2.2.4 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
SBSW — SIM Break Stop/Wait
15.2.2.5 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU
is in a break state.
Freescale Semiconductor
This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
BCFE
Bit 7
Bit 7
Bit 7
R
R
R
0
0
0
Figure 15-8. Break Flag Control Register (BFCR)
Figure 15-6. Break Auxiliary Register (BRKAR)
= Unimplemented
= Reserved
= Reserved
Figure 15-7. Break Status Register (BSR)
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
R
R
6
0
0
6
6
R
R
5
0
0
5
5
0
0
R
R
4
4
4
1. Writing a 0 clears SBSW.
R
R
3
0
0
3
3
R
R
2
0
0
2
2
Note
SBSW
R
1
0
0
1
0
1
(1)
BDCOP
Bit 0
Bit 0
Bit 0
R
R
Break Module (BRK)
0
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