MC908LJ24CFUER Freescale Semiconductor, MC908LJ24CFUER Datasheet - Page 262
MC908LJ24CFUER
Manufacturer Part Number
MC908LJ24CFUER
Description
IC MCU 24K FLASH 8MHZ SPI 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908LK24CFUE.pdf
(464 pages)
Specifications of MC908LJ24CFUER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908LJ24CFUER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Infrared Serial Communications
Data Sheet
262
Infrared Serial Communications Interface Module (IRSCI)
As the receiver samples an incoming character, it resynchronizes the RT
clock on any valid falling edge within the character. Resynchronization
within characters corrects misalignments between transmitter bit times
and receiver bit times.
Slow Data Tolerance
Figure 13-10
misaligned without causing a noise error or a framing error. The slow
stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit
data samples at RT8, RT9, and RT10.
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in
counts 154 RT cycles at the point when the count of the transmitting
device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 8-bit character with no errors is
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in
counts 170 RT cycles at the point when the count of the transmitting
device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
RECEIVER
RT CLOCK
shows how much a slow received character can be
MSB
154 147
------------------------- -
Figure 13-10. Slow Data
154
–
×
100
SAMPLES
DATA
Figure
Figure
=
MC68HC908LJ24/LK24 — Rev. 2.1
4.54%
13-10, the receiver
13-10, the receiver
STOP
Freescale Semiconductor
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