MC9S12XET256CAG Freescale Semiconductor, MC9S12XET256CAG Datasheet - Page 1035

• Manufacturer Part Number: MC9S12XET256CAG
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.3.2.7
The FSTAT register reports the operational status of the Flash module.
1. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
Freescale Semiconductor
ERSVIE1
ERSVIE0
Offset Module Base + 0x0006
DFDIE
Reset
SFDIE
Field
3
2
1
0
W
R
CCIF
EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error
is detected during an EEE operation.
0 ERSVIF1 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF1 flag is set (see
EEE Error Type 0 Interrupt Enable — The ERSVIE0 bit controls interrupt generation when a sector format error
is detected during an EEE operation.
0 ERSVIF0 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF0 flag is set (see
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see
1 An interrupt will be requested whenever the SFDIF flag is set (see
Flash Status Register (FSTAT)
1
7
= Unimplemented or Reserved
Table 27-16. FERCNFG Field Descriptions (continued)
0
0
6
Figure 27-11. Flash Status Register (FSTAT)
MC9S12XE-Family Reference Manual , Rev. 1.23
ACCERR
0
5
FPVIOL
0
4
Description
MGBUSY
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)
0
3
Section
Section
Section
Section
Section
RSVD
27.3.2.8)
0
2
27.3.2.8)
27.3.2.8)
27.3.2.8)
27.3.2.8)
0
1
(1)
MGSTAT[1:0]
Section
0
0
1
27.6).
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