MC9S12XET256CAG Freescale Semiconductor, MC9S12XET256CAG Datasheet - Page 194

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MC9S12XET256CAG

Manufacturer Part Number
MC9S12XET256CAG
Description
MCU 16BIT 256K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XET256CAG

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XE
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 3 Memory Mapping Control (S12XMMCV4)
3.1.5
Figure 3-1
3.2
The user is advised to refer to the device overview for port configuration and location of external bus
signals. Some pins may not be bonded out in all implementations.
Table 3-3
operation.
1. Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities.
194
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
EEEPROM
FLASH
Expanded modes
Address, data, and control signals are activated in normal expanded and special test modes when
accessing the external bus. Access to internal resources will not cause activity on the external bus.
Emulation modes
External bus is active to emulate, via an external tool, the normal expanded or the normal single
chip mode.}
External Signal Description
and
1
Block Diagram
shows a block diagram of the MMC.
Table 3-4
outline the pin names and functions. It also provides a brief description of their
MMC
BDM
MC9S12XE-Family Reference Manual , Rev. 1.23
EBI
Figure 3-1. MMC Block Diagram
Address Decoder & Priority
Target Bus Controller
CPU
RAM
XGATE
Peripherals
FLEXRAY
Freescale Semiconductor
DBG

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