HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 133

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The H8S/2600 CPU is driven by a system clock, denoted by the symbol ø.
The bus controller controls a memory cycle and a bus cycle. Different methods are used to access
on-chip memory and on-chip support modules. The bus controller also has a bus arbitration
function, and controls the operation of the internal bus masters: the CPU and data transfer
controller (DTC).
Note:
7.1
The period from one rising edge of ø to the next is referred to as a "state". The memory cycle or
bus cycle consists of one, two, three, or four states. Different methods are used to access on-chip
memory, on-chip support modules, and the external address space.
7.1.1
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 7.1 shows the on-chip memory access cycle.
The DTC, MMT, and POE are not supported in H8S/2614 and H8S/2616.
Basic Timing
On-Chip Memory Access Timing (ROM, RAM)
Internal address bus
Read
access
Write
access
φ
Figure 7.1 On-Chip Memory Access Cycle
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Section 7 Bus Controller
Bus cycle
Address
T
Rev. 7.00 Sep. 11, 2009 Page 97 of 566
1
Read data
Write data
Section 7 Bus Controller
REJ09B0211-0700