HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 287

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.3.5
The timer buffer registers (TBR) function as 16-bit buffer registers. The MMT has three TBR
registers; TBRU, TBRV, and TBRW, each of which have two addresses; a buffer operation
address (shown first) and a free operation address (shown second). A value written to the buffer
operation address is transferred to the corresponding TGR at the timing set in bits MD1 and MD0
in the timer mode register (TMDR). A value set in the free operation address is transferred to the
corresponding TGR immediately. Only 16-bit access can be used on the TBR registers; 8-bit
access is not possible.
11.3.6
The timer general registers (TGR) function as 16-bit compare registers. The MMT has nine TGR
registers, that are compared with the TCNT counter in the operating modes. Only 16-bit access
can be used on the TGR registers; 8-bit access is not possible.
11.3.7
The timer dead time counters (TDCNT) are 16-bit read-only counters. Only 16-bit access can be
used on the TDCNT counters; 8-bit access is not possible.
11.3.8
The timer dead time data register (TDDR) is a 16-bit register that sets the positive phase and
negative phase non-overlap time (dead time). Only 16-bit access can be used on TDDR; 8-bit
access is not possible.
11.3.9
The timer period buffer register (TPBR) is a 16-bit register that functions as a buffer register for
the TPDR register. A value of 1/2 the PWM carrier period should be set as the TPBR value. The
TPBR value is transferred to the TPDR register at the transfer timing set in the TMDR register.
Only 16-bit access can be used on TPBR; 8-bit access is not possible.
11.3.10 Timer Period Data Register (TPDR)
The timer period data register (TPDR) functions as a 16-bit compare register. In the operating
modes, the TPDR register value is constantly compared with the TCNT counter value, and when
they match the TCNT counter changes its count direction from up to down. Only 16-bit access can
be used on TPDR; 8-bit access is not possible.
Timer Buffer Registers (TBR)
Timer General Registers (TGR)
Timer Dead Time Counters (TDCNT)
Timer Dead Time Data Register (TDDR)
Timer Period Buffer Register (TPBR)
Section 11 Motor Management Timer (MMT)
Rev. 7.00 Sep. 11, 2009 Page 251 of 566
REJ09B0211-0700