HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 312

IC H8S MCU FLASH 128K 80QFP

HD64F2612FA20

Manufacturer Part Number
HD64F2612FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2612FA20

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
43
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2612FA20
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F2612FA20J
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 11 Motor Management Timer (MMT)
Bit
14
13
12
11 to
9
8
Rev. 7.00 Sep. 11, 2009 Page 276 of 566
REJ09B0211-0700
Bit Name
POE2F
POE1F
POE0F
PIE
Initial Value
0
0
0
All 0
0
R/W
R/(W) *
R/(W) *
R/(W) *
R/W
Description
POE2 Flag
Indicates that a high impedance request has been
input to the POE2 pin.
[Setting condition]
[Clearing condition]
POE1 Flag
Indicates that a high impedance request has been
input to the POE1 pin.
[Setting condition]
[Clearing condition]
POE0 Flag
Indicates that a high impedance request has been
input to the POE0 pin.
[Setting condition]
[Clearing condition]
Reserved
These bits are always read as 0. Only 0 should be
written to these bits.
Port Interrupt Enable
Enables or disables an interrupt request when 1 is
set in any of bits POE0F to POE3F in ICSR.
0: Interrupt request disabled
1: Interrupt request enabled
When the input set by bits 4 and 5 of ICSR
occurs at the POE2 pin
When 0 is written to POE2F after reading POE2F
= 1
When the input set by bits 2 and 3 of ICSR
occurs at the POE1 pin
When 0 is written to POE1F after reading POE1F
= 1
When the input set by bits 0 and 1 of ICSR
occurs at the POE0 pin
When 0 is written to POE0F after reading POE0F
= 1

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