HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 240

IC SUPERH MPU ROMLESS 112QFP

HD6417034AFI20

Manufacturer Part Number
HD6417034AFI20
Description
IC SUPERH MPU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417034AFI20

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417034AFI20
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417034AFI20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Direct Memory Access Controller (DMAC)
Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 2 States + 1 Wait State)
Rev. 7.00 Jan 31, 2006 page 212 of 658
REJ09B0272-0700
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = DRAM Bus Cycle
Figure 9.18 DREQ
Figure 9.19 DREQ
Bus cycle
Bus cycle
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA
DREQ
DACK
DREQ
DACK
CK
CK
transfer will be executed because the sampling is performed at the second state
of the DMAC cycle.
DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ
DREQ
DREQ
DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ
DREQ
DREQ
CPU
CPU
CPU
CPU
(Long Pitch Normal Mode))
CPU
CPU
Tp
T1
DMAC
DMAC (R)
Tr
Tw
Tc
Tc
T2
T1
CPU
DMAC (W)
DMAC (W): DMAC write cycle
DMAC (R): DMAC read cycle
Tw
Tp
T2
DMAC
Tr
CPU
Tc
Tc
DREQ Level
DREQ
DREQ
DREQ
DREQ
DREQ Level
CPU
CPU

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