HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 682

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Appendix B Pin States
Pin Name
CS7–CS2,
CS0
CS1
RAS
CASH
CASL
AH
RD
WRH
WRL
A0
A21–A1
AD15–AD8
AD7–AD0
DPH
DPL
R: Read
W: Write
—: The CS1 pin is used as the CASH signal output pin.
RAS: When a row address is output from A21–A0, an address strobe signal is output.
CAS: When a column address is output from A21–A0, an address strobe signal is output.
CASH: When a column address is output from A21–A0 during an upper byte access, an address
CASL: When a column address is output from A21–A0 during a lower byte access, an address
Parity: When a DRAM space parity check is selected with the parity check enable bits
Rev. 7.00 Jan 31, 2006 page 654 of 658
REJ09B0272-0700
strobe signal is output.
strobe signal is output.
(PCHK1,PCHK0) in the parity control register (PCR), this pin is used as the parity pin.
R
W
R
W
R
W
8-Bit
Space
High
Low
RAS
High
CAS
Low
Low
High
High
High
High
Low
A0
Address Address
High-Z
Data
High-Z
Parity
Upper
Byte
High
—
RAS
CASH
High
Low
Low
High
High
High
High
Low
A0
Data
High-Z
Parity
High-Z
2-CAS System
Lower
Byte
High
—
RAS
High
CASL
Low
Low
High
High
High
High
Low
A0
Address
High-Z
Data
High-Z
Parity
DRAM Space
Word
High
—
RAS
CASH
CASL
Low
Low
High
High
High
High
Low
A0
Address
Data
Data
Parity
Parity
16-Bit Space
Upper
Byte
High
Low
RAS
High
CASL
Low
Low
High
High
Low
High
High
A0
Address
Data
High-Z
Parity
High-Z
2-WE System
Lower
Byte
High
Low
RAS
High
CASL
Low
Low
High
High
High
High
Low
A0
Address
High-Z
Data
High-Z
Parity
Word
High
Low
RAS
High
CASL
Low
Low
High
High
Low
High
Low
A0
Address
Data
Data
Parity
Parity