HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 304

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
3. Set bits CMD1 and CMD0 in TMDB to select complementary PWM mode. TIOCA3,
4. Reset TCNT4 (to H'0000). Set the non-overlap offset in TCNT3. Do not set TCNT3 and
5. GRA3 is the waveform period register. Set the upper limit of TCNT3–1 * . Set the transition
6. Set the PFC for the external pin to be used.
7. Set the STR3 and STR4 bits in TSTR to 1 to start the TCNT3 and TCNT4 counts.
Rev. 7.00 Jan 31, 2006 page 276 of 658
REJ09B0272-0700
TIOCB3, TIOCA4, TIOCB4, TOCXA4, and TOCXB4 become PWM pins.
TCNT4 to the same value.
times of the PWM output waveforms in GRB3, GRA4, and GRB4. Set times within the
compare match range of TCNT3 and TCNT4.
Note: * GRA3 = [cycle count/2] + [count of non-overlaps] - 2cyc=[upper limit of TCNT3]-1
Note: To re-establish complementary PWM mode after it has been aborted, start settings from
T ≤ X
(X: initial setting of GRB3, GRA4, and GRB4; T: initial setting of TCNT3)
Figure 10.33 Procedure for Selecting Complementary PWM Mode
step 1.
Complementary PWM mode
Complementary PWM mode
Select complementary
Set general registers
Select counter clock
Stop counting
Start counting
PWM mode
Set TCNT
Set PFC
(4)
(1)
(2)
(5)
(6)
(7)
(3)