HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 452

IC SUPERH MPU ROMLESS 112QFP

HD6417034AFI20

Manufacturer Part Number
HD6417034AFI20
Description
IC SUPERH MPU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417034AFI20

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417034AFI20
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417034AFI20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 14 A/D Converter
14.4.3
With a built-in sample-and-hold circuit, the A/D converter performs input sampling at time t
after control/status register (ADSCR) access is started. See figure 14.5 for A/D conversion timing
and table 14.4 for A/D conversion times.
The total conversion time includes t
purpose of t
the duration of t
in table 14.4.
In scan mode, the ranges given in table 14.4 apply to the first conversion. The duration of the
second and subsequent conversion processes is fixed at 256 states (CKS = 0) or 128 states (CKS =
1).
Rev. 7.00 Jan 31, 2006 page 424 of 658
REJ09B0272-0700
Input Sampling Time and A/D Conversion Time
D
Input sampling
t
t
t
Notes: 1. ADSCR write cycle
is to synchronize the ADCSR write time with the A/D conversion process; therefore
D
SPL
CONV
D
A/D start delay
is variable. As a result, the total conversion time varies within the ranges shown
Input sampling time
Address
A/D conversion time
2. ADSCR address
timing
signal
Write
ADF
CK
Figure 14.5 A/D Conversion Timing
*1
*2
t
D
D
and the input sampling time, as shown in figure 14.5. The
t
SPL
t
CONV
D

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