HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 437

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

synchronizes internally with the falling edge of the start bit, which it samples on the base clock.
Receive data is latched on the rising edge of the eighth base clock pulse. See figure 13.21.
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation 2.
Equation 2:
This is a theoretical value. A reasonable margin to allow in system designs is 20–30%.
Synchronization
data (RxD)
base clock
sampling
sampling
M = 0.5 –
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L:
F:
D
M
Receive
Internal
timing
timing
Data
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
= 0.5, F = 0
= (0.5 – 1/(2
= 46.875%
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
2N
1
8 clocks
Start bit
– (L – 0.5)F –
(2)
16))
16 clocks
100%
–7.5 clocks
D
–
N
0.5
Section 13 Serial Communication Interface (SCI)
(1 + F )
+7.5 clocks
Rev. 7.00 Jan 31, 2006 page 409 of 658
100%
D0
REJ09B0272-0700
D1