UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 15

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 20 KEY INTERRUPT FUNCTION ......................................................................................689
CHAPTER 21 STANDBY FUNCTION...................................................................................................691
19.3
19.4
19.5
19.6
19.7
19.8
19.9
20.1
20.2
20.3
21.1
21.2
21.3
21.4
21.5
21.6
21.7
Maskable Interrupts ..............................................................................................................662
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
19.3.6
19.3.7
19.3.8
Software Exception ...............................................................................................................675
19.4.1
19.4.2
19.4.3
Exception Trap ......................................................................................................................678
19.5.1
19.5.2
External Interrupt Request Input Pins (NMI and INTP0 to INTP7) ....................................682
19.6.1
19.6.2
Interrupt Acknowledge Time of CPU...................................................................................687
Periods in Which Interrupts Are Not Acknowledged by CPU...........................................688
Cautions .................................................................................................................................688
Function .................................................................................................................................689
Register ..................................................................................................................................690
Cautions .................................................................................................................................690
Overview.................................................................................................................................691
Registers ................................................................................................................................693
HALT Mode.............................................................................................................................698
21.3.1
21.3.2
IDLE1 Mode ............................................................................................................................700
21.4.1
21.4.2
IDLE2 Mode ............................................................................................................................702
21.5.1
21.5.2
21.5.3
STOP Mode/Low-Voltage STOP Mode ................................................................................705
21.6.1
21.6.2
21.6.3
21.6.4
Subclock Operation Mode/Low-Voltage Subclock Operation Mode................................712
21.7.1
21.7.2
21.7.3
Operation................................................................................................................................. 662
Restore.................................................................................................................................... 664
Priorities of maskable interrupts .............................................................................................. 665
Interrupt control register (xxICn) .............................................................................................. 669
Interrupt mask registers 0 to 3 (IMR0 to IMR3)........................................................................ 671
In-service priority register (ISPR)............................................................................................. 673
ID flag ...................................................................................................................................... 674
Watchdog timer mode register 2 (WDTM2) ............................................................................. 674
Operation................................................................................................................................. 675
Restore.................................................................................................................................... 676
EP flag..................................................................................................................................... 677
Illegal opcode .......................................................................................................................... 678
Debug trap............................................................................................................................... 680
Noise elimination ..................................................................................................................... 682
Edge detection......................................................................................................................... 682
Setting and operation status .................................................................................................... 698
Releasing HALT mode ............................................................................................................ 698
Setting and operation status .................................................................................................... 700
Releasing IDLE1 mode............................................................................................................ 700
Setting and operation status .................................................................................................... 702
Releasing IDLE2 mode............................................................................................................ 702
Securing setup time when releasing IDLE2 mode ................................................................... 704
Setting and operation status .................................................................................................... 705
Releasing STOP mode/low-voltage STOP mode .................................................................... 709
Re-setting after release of low-voltage STOP mode................................................................ 710
Securing oscillation stabilization time when releasing STOP mode......................................... 711
Setting and operation status .................................................................................................... 712
Releasing subclock operation mode ........................................................................................ 716
Releasing low-voltage subclock operation mode ..................................................................... 716
Preliminary User’s Manual U18953EJ1V0UD
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