UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 234

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPnCCR0
register is transferred to the CCR0 buffer register.
cleared to 0000H, and a compare match interrupt request signal (INTTPnCC0) is generated.
(set value of TPnCCR0 register + 1) times.
234
When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is
The INTTPnCC0 signal is generated each time the valid edge of the external event count input has been detected
TPnCTL0
TPnCTL1
TPnIOC2
TPnIOC0
(a) TMPn control register 0 (TPnCTL0)
(b) TMPn control register 1 (TPnCTL1)
(c) TMPn I/O control register 0 (TPnIOC0)
(d) TMPn I/O control register 2 (TPnIOC2)
(e) TMPn counter read buffer register (TPnCNT)
The count value of the 16-bit counter can be read by reading the TPnCNT register.
TPnCE
Figure 7-11. Register Setting for Operation in External Event Count Mode (1/2)
0/1
0
0
0
TPnEST
0
0
0
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
TPnEEE
0
0
0
0
Preliminary User’s Manual U18953EJ1V0UD
0
0
0
0
TPnEES1
TPnOL1
0/1
0
0
0
TPnEES0 TPnETS1 TPnETS0
TPnCKS2 TPnCKS1 TPnCKS0
TPnMD2 TPnMD1 TPnMD0
TPnOE1 TPnOL0
0/1
0
0
0
0
0
0
0
TPnOE0
0
0
1
0
Select valid edge
of external event
count input
0: Disable TOPn0 pin output
0: Disable TOPn1 pin output
0, 0, 1:
External event count mode
0: Stop counting
1: Enable counting