UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 203

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Clock control register (CKC)
Cautions 1. The PLL mode cannot be used at f
Remark Both the CPU clock and peripheral clock are divided by the CKC register, but only the CPU clock is
The CKC register is a special register. Data can be written to this register only in a combination of specific
sequence (see 3.4.7 Special registers).
The CKC register controls the internal system clock in the PLL mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 0AH.
divided by the PCC register.
2. Be sure to set bits 3 and 1 to “1” and set bits 7 to 4, 2, and 0 to “0”.
3. Be sure to set the CKC register to 0AH. If a value other than 0AH is set, the operation is
After reset:
CKC
not guaranteed.
CKDIV0
0AH
0
1
0
f
Setting prohibited
XX
CHAPTER 6 CLOCK GENERATION FUNCTION
R/W
= 4 × f
0
Preliminary User’s Manual U18953EJ1V0UD
X
Address:
(f
Internal system clock (f
X
= 2.5 to 5.0 MHz)
0
FFFFF822H
X
= 5.0 to 10.0 MHz.
0
XX
1
) in PLL mode
0
1
CKDIV0
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