UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 82

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

82
(3) Restriction on conflict between sld instruction and interrupt request
(a) Description
(b) Countermeasure
If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld
instruction following an instruction in <1> and an interrupt request before the instruction in <1> is
complete, the execution result of the instruction in <1> may not be stored in a register.
Instruction <1>
Instruction <2>
<Example>
<i> ld.w [r11], r10
<ii> mov r10, r28
<iii> sld.w 0x28, r10
<1> When compiler (CA850) is used
<2> For assembler
• ld instruction:
• sld instruction:
• Multiplication instruction: mul, mulh, mulhi, mulu
mov reg1, reg2
satadd reg1, reg2
and reg1, reg2
add reg1, reg2
mulh reg1, reg2
Use CA850 Ver. 2.61 or later because generation of the corresponding instruction sequence can be
automatically suppressed.
When executing the sld instruction immediately after instruction <ii>, avoid the above operation using
either of the following methods.
• Insert a nop instruction immediately before the sld instruction.
• Do not use the same register as the sld instruction destination register in the above instruction <ii>
executed immediately before the sld instruction.
•
•
•
If the decode operation of the mov instruction <ii> immediately before the sld
instruction <iii> and an interrupt request conflict before execution of the ld
instruction <i> is complete, the execution result of instruction <i> may not be
stored in a register.
not reg1, reg2
satadd imm5, reg2
tst reg1, reg2
add imm5, reg2
shr imm5, reg2
Preliminary User’s Manual U18953EJ1V0UD
ld.b, ld.h, ld.w, ld.bu, ld.hu
sld.b, sld.h, sld.w, sld.bu, sld.hu
CHAPTER 3 CPU FUNCTION
satsubr reg1, reg2
or reg1, reg2
subr reg1, reg2
cmp reg1, reg2
sar imm5, reg2
satsub reg1, reg2
xor reg1, reg2
sub reg1, reg2
cmp imm5, reg2
shl imm5, reg2