UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 688

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UPD70F3737GC-UEU-AX

Manufacturer Part Number
UPD70F3737GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3737GC-UEU-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
84
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 12x10b, D/A 2x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3737GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
19.8 Periods in Which Interrupts Are Not Acknowledged by CPU
acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending).
19.9 Cautions
the NMI pin, validate the NMI pin with the PMC0 register. The initial setting of the NMI pin is “No edge detected”.
Select the NMI pin valid edge using the INTF0 and INTR0 registers.
688
An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be
The interrupt request non-sample instructions are as follows.
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (for PSW)
• The store instruction for the PRCMD register
• The store, SET1, NOT1, or CLR1 instructions for the following registers.
The NMI pin alternately functions as the P02 pin, and functions as a normal port pin after being reset. To enable
• Interrupt-related registers:
• Power save control register (PSC)
• On-chip debug mode register (OCDM)
Remark xx: Identification name of each peripheral unit (see Table 19-2 Interrupt Control Register (xxICn))
Interrupt control register (xxICn), interrupt mask registers 0 to 3 (IMR0 to IMR3)
n: Peripheral unit number (see Table 19-2 Interrupt Control Register (xxICn)).
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Preliminary User’s Manual U18953EJ1V0UD

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